DAC8812 Minimum time of CS pin is High

takishin

Expert 2360 points

Other Parts Discussed in Thread: DAC8812

Hi,

Our customer has a question about DAC8812.
I'm posting the question for a customer:

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We need to disable the DAC registers so LDAC pin is tied logic low.

We have one question.

How long is the minimum time when CS pin is the logic high state ?
(The time until a controller writes the next data )

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Thanks in advance.

Best regards,
Takishin

over 9 years ago

0 Eugenio Mejia over 9 years ago

TI__Genius 10615 points

Hi Takishin-san,

I'm glad I can be of assistance.

The minimum HIGH time for CS when LDAC is tied LOW, is 25 ns.

The datasheet is not very explicit about this timing specification. The timing calculation is: (t_lds) + (t_ldac) = 25 ns. I will see if it is possible for us to add this timing on a future datasheet revision.

0 takishin over 9 years ago in reply to Eugenio Mejia

Expert 2360 points

Hi Eugenio-san,

Many thanks for your assistance.

I will inform the customer of it.

Best regards,
Takishin

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DAC8812 Minimum time of CS pin is High