DAC8541 http://www.mouser.com/ds/2/405/slas353-117934.pdf is DAC8541 I need to know if CS being high always or never means data inputs (DB0-DB15)are Hi-Z, (tristate, 'disconnected') and/or, if using Note 4 above Figure 1 timing diagram, (CS and WR always low) means inputs (DB0-DB15) are Hi-Z all the while LDAC is High (assuming not during rising to input new data), or if they are Hi-Z while LDAC is Low, or ever at all. My need is to have a time when I/O is Hi-Z from Bus, and if either or both of the above ideas can achieve that, or some other idea (other than another buffer or driver chip) I will be grateful for an explanation or some guidance. I'd appreciate a couple samples, also, to experiment with, but now this is on E2E so where do I even ask? New to here. This is for a new proposed design to upgrade an existing prototype. Thank you.