ADS5402 Questions

Hi,

Yes, if the clock is set for DDR timing then if the rising edge is centered on a bit then the falling edge must also be centered on a bit.  And the clock would be 50/50 duty cycle or very close to it.  I will have to ask the datasheet author what was meant here.  In other devices I sometimes see the option in a SPI register to change the timing, such as to make the clock centered on the data valid window or to make the clock aligned with the data transitions.  I do not see such programmability in this register map, and I did not see such an option when I looked at the designers design spec.  So I will have to ask what was meant by this statement.

The SYNC output (and input) is meant for cases where the user wants to use a number of devices to implement a number of channels and needs to synchronize the samples from all of the devices later.  That is, if sample 'n' is latched into the FPGA from one device, then we want the FPGA to be able to match that sample up with sample 'n' from another channel instead of matching it up with sample n+1 or n-1.

The way we make provision for that is that there is a divide by 32 counter in the ADC that can output a SYNC signal that is the sample clock divided by 32.  If this divide by 32 is reset to the same phase in all ADCs at the same time on the same clock edge, then the SYNC output can be used to synchronize the data streams later.  There are several options described in the data sheet for using the SYNC input.  The SYNC input will reset the counter when the input is latched and seen to be 'high' after seeing that it was 'low' onthe previous clock edge.   This will reset the SYNC OUT counter.

If SYNC IN is a periodic signal, then if it resets the counter every 32 clock cycles then SYNC OUT is not disturbed - the signal is resetting the counter to the value that it already was going to be.   So that is why SYNCIN needs to be sample clock divided by 32, or divided by 64, etc. 

The period of SYNC out has nothing to do with the pipeline delay latency through the device.   The latency through the device could be 2 cycles or 102 cycles, doesn't matter.  The SYNC counter is still a divide by 32 and the SYNCOUT would be sample clock divided by 32.  Latency doesn't affect that.

The SYNC IN signal can be 'low' for any number of cycles and 'high' for any number of cycles, as long as the low-to-high portion of the signal is every 32 cycles, or every 64 cycles, or every 96 cycles, etc.

Regards,

Richard P.

Hi, this is a new question regarding the same device. Hi,
I am using ADS5402, 250Mhz clock. I can't get the sync output to be a square wave of 16 clks low, 16 clks high. The sync output of ADC seems to toggle randomly. I have tried giving the ADC chip both a pulse (4 clks, active high) sync input and a square wave input (16 clks high, 16 clks low).
This is the sequence of commands I did:1. Enable ADC2. Send SRESET
3. Spi write 0x8000 to register 0
4. a. If I provide a 4 clks high pulse sync input to ADC chip, I do the following:
Spi write 0x5554 to register 0x0ESpi write 0x5000 to register 0x0F
b. If I provide a square wave of 16 clks high, 16 clks low to ADC chip, I do the following:
Spi write 0xAAA8 to register 0x0ESpi write 0xA000 to register 0x0F
5. Spi write 0xFFFF to register 0x386. Spi write 0xFFFF to register 0x66
7. Spi write 0xFFFF to register 0x678. Spi write 0xDA1B to register 0x3A
9. Send sync input to ADC (either a 4 clks pulse active high signal or a continuous square wave with 16 clks high, 16 clks low)
10. Spi write 0x8202 to register 0x0111. Spi write 0x0000 to register 0x3C
12. Spi write 0x0000 to register 0x3D13. Spi write 0x0000 to register 0x3E
14. Set up to capture data in our FPGA FIFO.
We have 3ADCs hooking up to 1 FPGA. I tried to use different ADCs, and the results of sync output doesn't change (ie. togling randomly instead of a square wave).
When I turn off ADC sync output (by replacing steps 6 and 7 with writing 0xDFFF to reg 0x66 and reg 0x67), the sync output is 0.
I don't think we have any issue with our board routing or part contacts.
Would you please help me out with this issue? Without the sync output being a square wave, it's hard for us to line data up among the 3 ADCs.
Thank you,Vivian

Hi,

There was a bit description left out of the register map in the datasheet.  The datasheet is in the process of being edited so we will fix this.

Register address 0x01 bit D2 must be set to '1' to enable the SYNC output.   With this bit set to '0' which is default the output pin is set to output a portion of the sample data that is needed during device manufacture. 

Please set that bit and see if the expected SYNC pattern appears.  Then check to see that your three device all output SYNC at the same phase.  If not, we may need to look into the rules for setting the initial starting phase of the SYNC output.

Regards,

Richard P.

Hi Richard,Hi Richard,
Thanks for the reply. After I set bit D2 of reg 0x01 to '1', the sync out becomes square wave as expected. The 3 ADCs (with 6 sync out) seems to be in phase, but I need to collect more data to be more certain about this. I will follow up with more questions if neccesary.
Regards,Vivian