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OVR_SDOUT signal timing of ADS4146

Other Parts Discussed in Thread: ADS4146, SN74LVC1T45


I would like to ask you some questions about OVR_SDOUT of ADS4146 as below.

Q1) The timing

       I suppose there is not a detailed timing of this signal on the datasheet when this pin is used as "status signal".

       Could you tell me the timing? For example, ON/OFF timing, minimum pulse width(clock, Hz), etc

       And this signal is outputted by up-edge of CLK/M signal (=synchronized with input clock), right?

       The max signal frequency of this signal is 20MHz which is SCLK frequency, right? (in case of used as status, not interface.)

       I am planning to use ADS4146 as 130MHz DDR mode.

Q2) SIgnal level sift

       I am considering to use SN74LVC1T45 to change the signal level (1.8V to 2.5V or 3.3V).

       Is this possible to use?

Thank you for your support in advance.

Best Regards,