This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Problem with ADS8201 registers and in consequent interrupt

Other Parts Discussed in Thread: ADS8201

Hello,

I am currently debugging a board including the ADS8201 ADC.

The ADC is configured to start the conversion on /CONVST and to issue BUSY/INT. Sampling frequency is 320 Hz.

SPI SCLK is 4 MHz, here is the oscilloscope screenshot.

After the BUSY/INT pulse, the ISR starts and the sample is correctly read.

This is the "correct" acquisition, which is started and stopped by the routing below, by simply switching the parameter "EnDis":

void ADS8201Init(unsigned char EnDis)
{
unsigned char SpiData[2];

// reset

SpiData[0] = ADREG_WRITE | RST_SCR;
SpiData[1]= ADC_RESET;
BT_Serialize_SPI(SpiData, NULL_PTR, 2, 0, SELADC);

// idle mode

SpiData[0] = ADREG_WRITE | ADTRIG_SCR;
SpiData[1]= ADC_IDLE;
BT_Serialize_SPI(SpiData, NULL_PTR, 2, 0, SELADC);

// inputs configuration

SpiData[0] = ADREG_WRITE | CH01_CCR;
SpiData[1]= CH01_DIFF | CH0_POL_ODD;
BT_Serialize_SPI(SpiData, NULL_PTR, 2, 0, SELADC);

SpiData[0] = ADREG_WRITE | CH23_CCR;
SpiData[1]= CH23_DIFF | CH2_POL_ODD;
BT_Serialize_SPI(SpiData, NULL_PTR, 2, 0, SELADC);

SpiData[0] = ADREG_WRITE | CH45_CCR;
SpiData[1]= CH45_DIFF | CH4_POL_ODD;
BT_Serialize_SPI(SpiData, NULL_PTR, 2, 0, SELADC);

SpiData[0] = ADREG_WRITE | CH67_CCR;
SpiData[1]= CH67_DIFF | CH6_POL_ODD;
BT_Serialize_SPI(SpiData, NULL_PTR, 2, 0, SELADC);

// accurate 16 samples average, interrupt on INT/BUSY negative edge

SpiData[0] = ADREG_WRITE | ADC_SCR;
SpiData[1]= ACC_AVER_16 | INT_SEL_EDGE;
BT_Serialize_SPI(SpiData, NULL_PTR, 2, 0, SELADC);

// Interrupt on data ready

SpiData[0] = ADREG_WRITE | INT_SCR;
SpiData[1]= DATA_RDY_INT;
BT_Serialize_SPI(SpiData, NULL_PTR, 2, 0, SELADC);

// if enabled, triggger on /CONVST, always same channel

if (EnDis)
  {
  SpiData[0] = ADREG_WRITE | ADTRIG_SCR;
  SpiData[1]= MAN_TRG_MAN_CH;
  BT_Serialize_SPI(SpiData, NULL_PTR, 2, 0, SELADC);
  }

ADS8201RegDump();
}

As last instruction, the registers are read back and displayed in a debug screen.

It often happens that, trying to start and stop many acquisition sessions, the acquisition does not start at all, i.e. no BUSY/INT pulses are issues and the readback register values are different as shown in the table below.

register power up correct start  correct stop incorrect start incorrect stop Notes
CH01_CCR 0x00 0x0C 0x0C 0x0C 0x0C differential, odd polarity
CH23_CCR 0x00 0x0C 0x0C 0x0C 0x0C differential, odd polarity
CH45_CCR 0x00 0x0C 0x0C 0x0C 0x0C differential, odd polarity
CH67_CCR 0x00 0x0C 0x0C 0x0C 0x0C differential, odd polarity
CHSEL_CCR 0x00 0x00 0x00 0x00 0x00 sample CH1-CH0
ADC_SCR 0x00 0xF0 0xF0 0x00 0x00 16 samples accurate average, int on BUSY/INT neg edge
INT_SCR 0x00 0x00 0x00 0x00 0x00 write 1 to bit 0 to start
STATUS_SCR 0x00 0x00 0x00 0x00 0x00  
ADTRIG_SCR 0x02 0x02 0x00 0x02 0x00 manual trig/manual chan or idle
RST_SCR 0x00 0x00 0x00 0x02 0x00  
CVDEL_SCR 0x02 0x02 0x02 0x02 0x02  

Do you have any idea about the origin of such a behaviour?

Regards,

Jacopo

register power up correct start  correct stop incorrect start incorrect stop Notes
CH01_CCR 0x00 0x0C 0x0C 0x0C 0x0C differential, odd polarity
CH23_CCR 0x00 0x0C 0x0C 0x0C 0x0C differential, odd polarity
CH45_CCR 0x00 0x0C 0x0C 0x0C 0x0C differential, odd polarity
CH67_CCR 0x00 0x0C 0x0C 0x0C 0x0C differential, odd polarity
CHSEL_CCR 0x00 0x00 0x00 0x00 0x00 sample CH1-CH0
ADC_SCR 0x00 0xF0 0xF0 0x00 0x00 16 samples accurate average, int on BUSY/INT neg edge
INT_SCR 0x00 0x00 0x00 0x00 0x00 write 1 to bit 0 to start
STATUS_SCR 0x00 0x00 0x00 0x00 0x00  
ADTRIG_SCR 0x02 0x02 0x00 0x02 0x00 manual trig/manual chan or idle
RST_SCR 0x00 0x00 0x00 0x02 0x00  
CVDEL_SCR 0x02 0x02 0x02 0x02 0x02