ADCs and metastability

Hi,

Some of our datasheets have BER or CER (bit error rate or code error rate) specified, but many do not.  But we have measured BER on many of our devices.   The error rate is *strongly* dependent on the exact sample rate, because a slower clock period means a longer time for the comparators to settle to a value before they are latched for output.   For this reason we would usually measure the error rate at the datasheet max sample rate for worst case unless there was a request for a specific sample rate, and we often would not put the worst case error rate in the datasheet as it may be misleading for a customer looking at something less than the max sample rate.   I suppose a curve of error rate vs sample rate in the section with all the typical performance plots would be good, but measuring the error rate at a single point is a long process; making a curve of such points woule be more so.

You mention a list of devices with the qualifier 'such as'.   As different people are responsible for different part numbers, i would suggest pinning down the specific devices you would want the error rate on and posting a request for one device at a time so the right support person could take ownership of the request.  The devices you do mention as examples are from widely different families of design.

I might mention also that the error rate does arise from the comparator settling time to resolve in a stage of flash ADC.  Since we make pipelined ADCs, any such error would be in one of the ADC stages and so the error bit would be seen in only a few locations in the sample.  Not every bit in a sample can be expected to be in error with some probability.  If you were to look at the block diagram of a pipelined ADC (front page figure in the ADS5474 datasheet is one such example) you could see that any error in the first stage of the pipeline would be the worst and would always show up in maybe bit 10 of a 14 bit sample possibly, or an error in the second stage might always show up in bit 6 of a 14 bit sample, while an error in the final stage would be virtually un recognizable at all from the noise floor.  Just FYI.

Regards,

Richard P.

Hi

Thank you for the thorough answer.

I admit that specified devices are from different families. But now I don't need the concrete data. I would like to know the approximate error probability for these ADCs operating on the maximum frequency of 200-250 MHz. Is it 1E-9 or 1E-12 or 1E-15?

Regards,

Oleg