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Question on ADS1274 SPI Interface(Third question)

Hak-Jin Jeong
Intellectual 350 points

Other Parts Discussed in Thread: ADS1274

Hello,

This might be the last question on ADS1274 SPI Interface.

In SPI mode (not Frame-sync mode), Is there any sync requirement between SCLK and CLK?

From one of posts in this comunity, I saw sync might be required for better performance even in SPI mode.

( not only ratio requirement(1:1, 1:2. 1:4. 1:8) between SCLK and CLK)

But, I cannot find any sync  timing requirment between SCLK and CLK) except ration requirement in real ADS1274 datasheet)

So, currently, my plan is to use external oscillator(20.48MHz) for CLK input,

and same clock (or half clock of CLK) from DSP will be provided to SCLK input.

Will it be okay?

If sync between SCLK and CLK is required, I have no ideda how to fullfil sync requirement,

DSP should be SPI master, and how can DSP provide continuous CLK (sync-ed SCLK) as well as SCLK?

Please let me know your advice.

Best Regards

Hak-Jin Jeong

  • 0
    TI__Guru 68316 points

    Hello Hak-Jin,

    I do not recall a phase relationship necessary between CLK and SCLK. The ratio of their frequencies (SCLK/CLK) has shown to affect noise performance, where ratios of 1:1, 1:2. 1:4. 1:8, etc. give the best results. However, ratios other than 1 / 2^n will still meet datasheet noise performance.

    Best Regards,