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DAC38J82 DAC PLL configuration

Shant Moses
Prodigy 160 points


Hi,

I am trying to bring-up a software driver for this part and I came across the DAC PLL configuration step. There is no enough information in the datasheet about the recommended PFD frequency operating range and how the pll_cp_adj should be calculated for a certain PFD frequency. Can someone please help with this question?

Regards,

Shant

  • 0
    TI__Guru* 79364 points

    Hi Shant,

    In general we want to keep the PFD frequency of the on-chip PLL to be within 500MHz (the specification by design is about 625MHz). We usually start our charge pump current from about 0.5mA and continue to increase until the phase noise corner are pushed out far enough from the carrier. When charge pump current increases too much, the phase noise corner may peak and cause stability issues. 

    If you can let me know your desired DAC on-chip setup (i.e. reference clock to the PLL and the desired DAC sample rate), I can set up the DAC in the lab and let you know the optimal phase noise and settings.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 160 points
    Hi Kang,

    This is about the range that I'm trying to run the PFD at (500-625) MHz for DAC sample rates of (2GSPS - 2.5GSPS).

    Currently, I'm setting the pll_cp_adj to 12 and the memin_pll_lfvolt reads back 3-4.

    Regards,
    Shant