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ADS7044 Sample&Hold timing

Other Parts Discussed in Thread: ADS7044

Hi, folks

1) Sample and hold exact timing

I would like to know exact sample&hold timing which sw is described in figure 33.

I guess close timing(Sample) is @(posedge 14th of SCLK) and open timing (Hold)  is @(negedge CS).

Am I correct?

This is for simultaneous sampling between channels (We would like to use at least 2 of ADS7044s)

2) Offset cancellation circuitly

I guess that the sample & hold switches are opened and channel inputs are shorted internally

and then converted so that stores value as OCR to be add&subs from next meaurement result.

Am I correct?

Also if offset cancel in normal operation, I can read the sample&hold switch close @(negedge CS) and open @(posedge CS)

from spec sheet. Am I correct also?

I am bit colusing because the close timing is slighetly different in each cases.

  • Keiichi-san,

    Your interpretation of the timing diagrams and the operation of the ADS7044 is correct.

    The device enters acquisition mode (Sample) at end of the current conversion and captures the input signal (Hold) for the next conversion at the negedge of CS. In case you wish to simultaneously sample across multiple ADS7044s, the CS can to be driven simultaneously.

    In offset calibration during normal operation, the switches are internally connected at the 17th SCLK falling edge and offset value is stored at the 32nd SCLK edge. The next sample is captured (Hold) at the negedge of CS (I guess this was a typo in your post).

    As long as the tD_CKCS>10ns and tACQ>200ns specs are met, the device will operate as expected.



  • Sandeep

    Thank you for your reply. I understood.