Hi, folks
1) Sample and hold exact timing
I would like to know exact sample&hold timing which sw is described in figure 33.
I guess close timing(Sample) is @(posedge 14th of SCLK) and open timing (Hold) is @(negedge CS).
Am I correct?
This is for simultaneous sampling between channels (We would like to use at least 2 of ADS7044s)
2) Offset cancellation circuitly
I guess that the sample & hold switches are opened and channel inputs are shorted internally
and then converted so that stores value as OCR to be add&subs from next meaurement result.
Am I correct?
Also if offset cancel in normal operation, I can read the sample&hold switch close @(negedge CS) and open @(posedge CS)
from spec sheet. Am I correct also?
I am bit colusing because the close timing is slighetly different in each cases.
