Hi,
I am using ADS5402, 250Mhz clock. I can't get the sync output to be a square wave of 16 clks low, 16 clks high. The sync output of ADC seems to toggle randomly. I have tried giving the ADC chip both a pulse (4 clks, active high) sync input and a square wave input (16 clks high, 16 clks low).
This is the sequence of commands I did:
1. Enable ADC
2. Send SRESET
3. Spi write 0x8000 to register 0
4. a. If I provide a 4 clks high pulse sync input to ADC chip, I do the following:
Spi write 0x5554 to register 0x0E
Spi write 0x5000 to register 0x0F
b. If I provide a square wave of 16 clks high, 16 clks low to ADC chip, I do the following:
Spi write 0xAAA8 to register 0x0E
Spi write 0xA000 to register 0x0F
5. Spi write 0xFFFF to register 0x38
6. Spi write 0xFFFF to register 0x66
7. Spi write 0xFFFF to register 0x67
8. Spi write 0xDA1B to register 0x3A
9. Send sync input to ADC (either a 4 clks pulse active high signal or a continuous square wave with 16 clks high, 16 clks low)
10. Spi write 0x8202 to register 0x01
11. Spi write 0x0000 to register 0x3C
12. Spi write 0x0000 to register 0x3D
13. Spi write 0x0000 to register 0x3E
14. Set up to capture data in our FPGA FIFO.
We have 3ADCs hooking up to 1 FPGA. I tried to use different ADCs, and the results of sync output doesn't change (ie. togling randomly instead of a square wave).
When I turn off ADC sync output (by replacing steps 6 and 7 with writing 0xDFFF to reg 0x66 and reg 0x67), the sync output is 0.
I don't think we have any issue with our board routing or part contacts.
Would you please help me out with this issue? Without the sync output being a square wave, it's hard for us to line data up among the 3 ADCs.
Thank you,
Vivian
