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ADS5463 EVM Data errors

Ethan McClure
Prodigy 30 points
Other Parts Discussed in Thread: ADS5463

I recently attached a ADS5463 EVM board to a Altera Cyclone V GX board via HSMC-ADC bridge.  This Cyclone GX acquires data on the positive edge of each clock cycle (125 MHz) for about 30 samples.  Then sends the data serially to MATLAB, which I've checked is working correctly.  I believe I've set up the ADS5463 board correctly, 5V and 3.3V where necessary, I'm seeing the correct currents to each input as well.  My clock signal is coming in at 125 MHz at about 1.5V pk-pk, and my input signal is at 10MHz.  When I send the signal at 2V pk-pk the signal is relatively accurate but there is saturation at the mins/maxs.  As I decrease the sine wave to 1.5V or less there are significant errors.  The output is often so noisy that the general shape of the sinusoid is hard to find.  Most often the bits that seem to be incorrect are 4,5,7 and sometimes 8,9. But sometimes there is a data point that is an outlier that is completely off from the set.  Not sure if I'm reading the data incorrectly on the FPGA, I have the inputs coming in as LVDS inputs.  Where could these errors be coming from?

  • 0
    TI__Mastermind 29220 points

    Hi,

    I would have to see an example of what you are describing, but your description of the FPGA latching data on th epositive edge of the clock cycle concerns me.  The LVDS clock that is intended to be used to latch the data is the DRY signal, and it is a source-synchronous dual data rate clock.   The rising and falling edges of the DRY signal is to be used to latch the sample data, and the DRY signal must be delayed or shifted by 90 degress before being used to latch the data.      The timing of the data and DRY signals as it leaves the ADC is that the rising and falling edges of DRY are aligned with the data transitions (to within some skew tolerance) such that there is no valid setup and hold time for the data around the DRY edges.   Figure 1 of the datasheet illustrates this.  In our TSW1400 capture card which also uses an Altera FPGA the DRY signal goes to a PLL that does a 90 degree shift of DRY and then uses that to latch the input DDR cells.

    Regards,

    Richard P.