ADC08B200 lowest sampling rate

Hi Kratochvil T.

I'm looking into this and should have a response for you tomorrow.

Regards,

Jim B

Hi again

Given the numerous references to a 15 MHz minimum clock rate in other sections of the ADC08B200 datasheet, I believe that 22.5 MHz CLK frequency will be OK.

Are you using the PLL frequency multiplier (2x, 4x or 8x), or will 22.5 MHz be the actual sampling rate?

Best regards,

Jim B

Does it make difference? I plan to take sampling rate clock from operating MCU.

Thank you for your answer!

I have another question:
Do you know about any other ADC with higher buffer memory(>1kB)? Or any kind of parallel to USB converter? (8bit 22,5 MHz sampling rate, one channel)

Best regards,
Tomas Kratochvil

Hi Tomas

The ADC should function with the 22.5 MHz clock coming from  the MCU. The SNR and SFDR performance may be degraded due to the amount of jitter and harmonic noise on the MCU clock as compared to a clean 22.5 MHz oscillator module.

I don't know of any other 22.5MSPS capable ADCs with a larger buffer size, or any simple 22.5MSPS ADC to USB type devices.

Regards,

Jim B