ADS5282 along with FMC-ADC adapter in spartan 6 device

Sent to the address provided.

Regards,

Richard P.

Hi Simon,

how do you connect the afe5801evm ad the spartan6 board?

I have the afe5851 and to connect with the spartan6 board I buy the texas adapter card (http://www.ti.com/tool/fmc-adc-adapter). The problem is that the samtec connector of the afe5851 has 80 pins, instead the samtec in the adapter card has 120 pins, so I can't connect then. How I can do to connect the two board?

Thank you

Hi,

The AFE5801 is supported by our Medical and High Reliability group.  The original posting in this thread was regarding an ADS5282 which *is* supported in the High Speed Data Converters forum.   I see that you also found a posting in the Medical and Hi Rel forum to append to, so I trust that you will get support in that forum.

That said, there is an adapter card available from the Medical and HiRel group that bridges the 80 pin Samtec connector pinout to the 120 pin Samtec connector pinout.  I've see it and used it, but I do not have access to the schematic or design documents for it.  I will have to let the HiRel group address that.

Regards,

Richard P.

Hi Richard,

Same like the others, I am conencting spartan-6 to ADS62P49EVM through the ADC FMC adapter. I will really appreciate it if you can send a copy of Verilog source code of the TSW1200 to:

cjomoreira@gmail.com

Thank you very much.

Sent to the address provided.

Regards,

Richard P.

I saw in other forum texas that for the capture card TSW1200 exist some matlab scripts that allow to capture more than one channel togheter. This could be very important for us with the TSW1250, because we need to capture 4 channel togheter.

Regards,
Rino

Hi,

The TSW1250 is supported by our Medical and High Reliability group.  The forum for them is simply called High Reliabilityi believe, so you might not know to go to that forum.  The TSW1250 is the same hardware as the TSW1200 but the FPGA firmware is different to support their devices and the USB port is programmed to appear as TSW1250 to the PC adn so the TSW1200 GUI would not work with the TSW1250.  The Matlab code for TSW1200 should easily port over to the TSW1250 *if* they didnt also change the register map in the FPGA when they created new firmware.  But the Medical group would have to be the group to support this.  I will try to split this thread and move this over to that forum.

Regards,

Richard P.

I'm working on  connecting the ADC to a Virtex-4 device ,and really confused .
so can you also send me a copy of the verilog code of TSW1200,please,many thanks

330623292@qq.com

Hi Richard,

Could be possible to acquire with the matlab code in externel trigger mode?

Is there any matlab code to work in this mode? I think that the knowledge of the trigger register's could help us.

Thanks,

Rino

Hi Richard,

Could you please send me a copy of the Verilog source code to yairlinn [at] triumf.ca ?  I am interested in connecting an ADS5282 to a Spartan-6 device.

Thanks in advance!

Yair

Sent to the address provided.

Regards,

Richard P.

Richard,

I am also looking for example interfacing code for the vsp7500 which is similar as ADS5282EVM .  Verilog code for the TSW1200 would be great; would it be possible to get a copy?  My email is chenju2181@sina.com.

Thanks in advance.

Sent to the address provided.

Regards,

Richard P.

Dear Richard,

I am also trying to interface ads5282evm with my Spartan-6 FPGA board but I am using VHDL. It would be really really nice if you could provide me a copy of the Verilog code for tsw1200 that you have. This will definitely be a great example of how I can deal with the ADC with LVDS interface. Thank you very much indeed and my email address is roengrut@yahoo.com

Regards,

RR

_{Hi,
sent to the address provided.}

_Regards,

_{Richard P.}

I've recently bought a SP605 xilinx eval board and an ADS54RF63EVM ADC eval module (along with the ADC to FMC passive adapter board).  I'd like to capture ADC output and send it out of the gigabit ethernet interface on the sp605.  Would the code you are providing here help with that?  Could you please send it to me so I can evaluate it?  Thanks!

- ben.

buhrow.benjamin@mayo.edu

Hi,

i sent the source code for the parallel data format (as that is the code for the part number you called out) to the address provided.  You would need to do some editing to port over the ADC interface portion of the code, but i also sent a sketch of how i use the IDELAY and IDDR cells to meet timing into the FPGA.  You would need to determine what your IDELAY tap settings would need to be to meet timing,and you would need to edit the constraint file to match the pinout you will end up with into your FPGA.  Much of the code is the buffer memory and a simple UART port to move the captured data out of the FPGA.  You would need to put your code for that in place of what you find there.

Regards,

Richard P.

Hello Richard,

I am try to interface ADC ADS54RF63 with Xilinx FPGA.

Please send me VHDL/Verilog source code for TSW1200.

My e-mail: galkin@eltesta.com

Thank you in advance.

Hi,

sent to the address provided.

Regards,

Richard P.

Hi Richard,

I would appreciate if you could share with me with your code. Thanks in advance. My email is logison@o2.pl

Best Regards,

Mariusz

Hi,

Which ADC EVM would you be using?  I have to ask the same question I ask everyone else who doesn't say what it is they are asking for.  The TSW1200 has two bit files stored in the eeprom on the board and consequently there are two different source code folders.  One is for the LVDS DDR parallel bus interface and the other is for the serialized data format.  Both formats have been mentioned in this thread already so I don't know which one you are asking for.

Regards,

Richard P.

Hi Richard,

I'm going to use AFE5808 on my custom board and interface it to XC6SLX45 FPGA, so I have LVDS DDR serialized data format and deserialize it.

Regards,

Mariusz

Hi Richard,

Till now I haven't got received any message from you. I would be very appreciated of sharing the code for deserialization of LVDS DDR incoming data. Application: ultrasound scanner based on AFE5808 .

My email is: logison@o2.pl

Thanks in advance,

Mariusz

Hi,

sent to the address provided.

Regards,

Richard P.

Hi Richard,

Thanks a lot for your kind support.

Best Regards,

Mariusz

Hi Simon,

Shame to say on me, I'm not so familiar on VHDL. I rather prefer schematics drawing. For my application, I need to use just only one channel of AFE5801. Can you please simplify your VHDL design and show it to the forum ?

I mean about something like this:

Inputs:

- FrameClk_P/ FrameCLK_N  (I'm sure you understand what I mean)

- Serial_Data_In_P(0)/Serial_Data_In_N(0) - same as above, however, I want to use just only ONE channel of AFE5801.

- Bit_CLK_P/Bit_CLK_N (I'm sure you understand what I mean)

Outputs:

Just only :

Deserialized_Output_Is <= Something_well_captured(11 downto 0);

I'm sure, you understand the above pseude-code. Your advice will be VERY appreciated.  Please, be so kind of answering within this threade!! Your intelectual support will be very helpfull!!

Best Regards,

Mariusz

Hi Dear Richard

I am also trying to interface ads5282evm with my Spartan-6 FPGA SP601 board  It would be really really nice if you could provide me a copy of the Verilog code for tsw1200 that you have.   my email address is qing.he@newport.com

Thanks very much.

QH

Sent to the address provided.

Regards,

Richard P.

Hi Richard,

According to the crash on my HDD, I kindly would like to ask you for resending the file.

My email:  logison@o2.pl 

Thanks in advance,

Best Regards,

Mariusz

Resent.

Regards,

Richard P.

Dear Richard,

If possible I would like very much to receive the Verilog code for the LVDS version of TSW1200 code. I hope consulting the code will speed up my development efforts.

Regards

Pawel K.

and in case my login (email) is not visible, here is the address: pkopyt@elka.pw.edu.pl

sorry for severel mails on the same subject...

Pk

Sent to the address provided.

Regards,

Richard P.

Dear Richard,

Many thanks again for the code, which together with its modification (code for TSW1250) provided a good starting point for me. I have a small question that is hardware-specific . I'll appreciate very much if you could shed some light...

While analysing your work I found that you explicitely defined the following routing for the DDR clock that turns your shift reg's (module ddrif_data_path_iobs_0):

DDR_DQS -> IDELAY -> BUFIO -> BUFR -> shift reg's...

Out of curiosity I checked the structure of Virtex-4 only to find that the pins that you use for the DDR_DQS (B19 and C20) are regional clock-capable (IO_L8P_CC_LC_5, IO_L8N_CC_LC_5). Thus, the IDELAY located in such IOB's:

(an excerpt from the virtex4-hdl.pdf, p. 121)

My question: if the IDELAY located in these IOB's can connect directly to the logic turning shift reg's (aka "your logic"), why did you opt for a bunch a additional buffers, if the signal outputed by the IDELAY is not used anywhere else for driving anything except for the registers?

Your answer will help me understand Xilinx's FPGA's much better than now.

Best regards

Pawel Kopyt

Hi,

I can't view the excerpt from the virtex document, so I don't know quite what the question is.   Some types of items don't post very well in this forum.

But that particular signal pair you pointed to is the DDR bit clock for the serialized data, and so the clock has to go to the clock input of a number of logic cells within the FPGA.  I did *not* use the ISERDES element that was there, mostly because I wanted to have the flexibility to create my own 'load pulse' to control a mux in front of the register that catches the deserialized data.  This makes the logic flexible for different serialization factors.  I have serial formats where the 'load pulse' I create from the Frame Clock low-to-high position may come along every four bits, every six bits, every 8 bits or every 12 bits.  This logic always loads the last 16 bits into the parallel register regardless of the serialization factor, so if it is a 12bit serializer then I just use 12 bits out of the register and throw away the other 4, as they are redundant with four bits from the previous cycle.    I built my deserilizer inside the FPGA fabric, not just in IOB cells, so I think I needed to buffer the clock to a region accordingly.  Also - I was workingto modify a design from a prson who had written the code ahead of me and I left the clocking alone.  This code base has the same clock buffering as the parallel DDR code base that is also used in the TSW1200 and in that code the clock *does* go into the FPGA to clock data into a FIFO.

Keep in mind the caveat that I always include when I send out the code - the code is more complicated than it otherwise might need to be since the TSW1200 has to serve many different EVMs.  If we knew the code would only ever have to accept data from an ADS5282 for example, then the code could simplify down somewhat.

Regards,

Richard P.

Hi!

Many thanks for the response, the patience and time. For the sake of completeness the excerpt from the V-4 documentations reads:

(...)Regional Clock-Capable IOBs - Regional clock-capable IOBs are located in one I/O pair directly above and
below an HCLK IOB. The input of IDELAY in a regional clock-capable IOB comes directly from the input
buffer, IBUF. The output of IDELAY in a regional clock-capable IOB can go to one of the following locations:

• Directly to your logic
• BUFIO (in the case of a regional clock signal)

(...)

My fault was to be lazy and not copying and reformatting text, but instead pasting the PrtScr, which did not work.

Anyway, thank you for the explanation. I was just curious, and there is no better way of learning like observing verenans at work. I do realize that this code is layers upon layers of work of various people. Some of the details are important while others come simply from preferences of consecutive authors. When looking from outside sometimes it is tough to tell which of the two cases is... the case.

As for the code, I have compared several codes for DESER job so far, and I find yours the most streight-forward and light on resources. No awkward dedicated primitives that at the end must be cascaded, no overlly complex state machines just to find one frame-clock transition etc. Looks like good and useful work.

Many thanks

Pawel Kopyt

Hi Richard,

Could you please send me a copy of the Verilog code. kmpday001@myuct.ac.za

Thanks,
Dayne

Hi,

Sent to the address provided.

Regards,

Richard P.

Hi Robert,

Firstly, thanks for sending me the Verilog code.

I have a question regarding the implementation of the "SERDES" aspect of the code. Is your method limited in terms of input bit rate more so than those that use dedicated I/O primitives such as ISERDES? 

Lastly, for any given setup do the delay "blocks" have to be dynamic or can they be fixed once the optimum delay has been determined? 

Thanks.

Hi,

That's a good point, actually.  The IDDR cells on the Virtex4 were rated to 1000Mbps data rate with the clock max at 500MHz, but that presumes a certain amount of setup and hold time that the source of the data would need to provide to the FPGA.  If the source of the data takes up too much of the bit timing budget for its own skews and gives the FPGA less setup/hold time that the IDDR wants to see then the actual max data rate would be less.  The dedicated primitives like the ISERDES could probably achieve a higher data rate.   But our TSW1200 had eeprom space for only two bit files and one of those bit files was for the non-serial DDR format.  The other bit file had to support all the serial formats and the way i did it was flexible.  We didnt have dynamic partial reconfigurability of a bit file at run time back then so the firmware had to be flexible.  That flexibility is also why we used the dynamic mode of the IDELAY - because we wanted to write a tap setting for clock delay or data delay to accomodate many different EVMs.  Your design could just use the static timing analysis to determine the best timing for the IDELAY and lock that down permanently.

Regards,

Richard P.

Hi Richard,

If possible to take up some of your time, I have another question somewhat related to the ADS comm, but (probably) more so to the timing constraints that need to be defined on the Data_In Time group (p/n pins from the ADS528x ADC). You wrote that (ADS5463.ucf)

TIMEGRP DATA_IN OFFSET = IN 0.465 ns VALID 0.89 ns BEFORE DDRClk_p_pin TIMEGRP FF_RISING;

This is perfectly in-line with the specs for ADS528x, and the expected bit-rate (6 x 65MSPS is close to 400 MHz or 2.5ns period). I am, however, struggling to read the other constraint:

TIMEGRP DATA_IN OFFSET = IN -0.785 ns VALID 0.89 ns BEFORE DDRClk_p_pin TIMEGRP FF_FALLING;

I wonder if you could explain maybe or at least point me to the right direction... This looks like that validity window for data occurring at the falling edge conicides exactly with the validity window of data occuring at the next raising edge. I run a google search for such a construct but all the cases I'have found are rather straigh-forward, and with no such surprises.

Many thanks in case you find some time to drop a line.

Regards

Pawel Kopyt

Hi,

I would suggest going to the FPGA vendor's forum for questions on the timing constraints.  Back when the TSW1200 Capture Card was being developed, we found the timing constraint to be not very intuitive for source-synchronous DDR timing and one of our first guys working on it got a Xilinx guy to come out and write the timng constraints for us.  That was for something like version 9 of their ISE tools.  Those old tools were not Windows7 compatible and we have had to go to the new tools since then and I have been told that the constraint format is not quite the same, so I don't know how helpful the old constraint file would be. 

Also, if you are trying to match up the numbers you see in the constraint with current datasheet on the TI web for that device - the development of the TSW1200 happened before the ADS5463 went to production so we only had preliminary timing numbers at that time.  The numbers had changed slightly since the constraint was written - so that might add some confusion too.

Regards,

Richard P.

Hi,

I am trying to interface AFE5805EVM to Zynq. Can you share me the code for deserializer? I have tried xapp524. I get the issue similar to one described in xilinx forum.

email : jothiadithya@gmail.com

Regards,

N Jothi

Hi Richard,

I am looking for the  vhdl/verilog code of the TSW1200, can you send me a copy?  My email is jothiadithya@gmail.com

Jothi 

Hi,

As explained in separate email, the AFE device you called out is supported by the TSW1250 from our Medical Group rather than the TSW1200 from the High Speed Data Converter group.  Still, i have sent the Verilog code for the serial data format for the TSW1200 as the deserialization approach will be very similar.

Regards,

Richard P.

Hi Richard,

Thank you. received the code.

Jothi

Hi Richard,

Could you send me the HDL code of the TSW1200. My email is thomas.carmignani@firstlight.fr

Regards

Thomas

Hi,

Sent to the address provided.

Regards,

Richard P.

Hi Richard,

I have received the code

thank you so much.

Regards

Thomas