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ADS5527: input clock signal

emilio arnieri69
Prodigy 110 points

Other Parts Discussed in Thread: ADS5527

I’ve developed a clock distribution network to feed 60 ADS5527. I’ve used LVDS signal. At the clock distribution network output I’ve obtained the waveform shown in the attached figure. Is this clock waveform acceptable for ADS5527?

  • 0
    TI__Guru* 91947 points

    Emilio,

    We are looking into this and will get back with you ASAP.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Guru* 91947 points

    Emillio,

    The minimum Input clock amplitude differential (V(CLKP) - V(CLKM)) is 0.4V. After looking at your clock waveform, it looks like this value is ~ 0.32V. To meet the data sheet specification, you will need to increase this amplitude. The part may work with this level of clock amplitude, but it will not be guaranteed.

    Regards,


    Jim

  • 0 in reply to jim s
    Prodigy 110 points

    Dear Jim,

    thank you for the useful information.

    Following your suggestion I've updated the clock distribution network in order to increase the amplitude of the input clock (LVDS). The attached figure shows the new waveform observed at the input of the ADS5527. Is this clock waveform acceptable for ADS5527?

    Regards,

    Emilio

  • 0 in reply to emilio arnieri69
    TI__Guru* 91947 points

    Emilio,

    If the frequency is 210Msps or below and at least 0.4V p-p, and the duty cycle between 35% to 65%, it should work. I cannot tell the duty cycle of your waveform, but the amplitude and frequency appear correct.

    Regards,

    Jim