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ADC0xD1520RB - Question for TI Support

Mircea Bogdan
Intellectual 370 points

Other Parts Discussed in Thread: ADC07D1520

Hello,

I'm designing a new module with 4 chips ADC07D1520, and one FPGA, and I'm using the ADC0xD1520RB as reference.

Looking at the ADC0xD1520RB schematic page 11, it seems to me that the ADC power 1V9A comes up some 55ms after 1V8IO power, which supplies the FPGA ADC IOs.

Is that correct?

If that is correct, the ADCs connect to the FPGA, and the FPGA IOs come to life sooner than the ADC is powered, right?

This appears to be in contradiction to the ADC07D1520 data sheet, which states at page 44:

"Be sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than does the voltage at the ADC07D1520 power pins."

Is that a mistake in the DB schematic, or what am I missing here?

Anyway, I'm thinking to power the Vdr of the ADC07D1520 at the same 1.8V power rail as powers the corresponding FPGA IO bank, and to start this 1.8V power only after the FPGA core power comes up. So, the Vdr  will come up later than Va for the ADC chip.

On the other hand, Va will start without delay, and after Va is up, the Front End power gets enabled.

Please, give me your opinion about this option.

Thanks,

MIrcea

  • 0
    TI__Mastermind 44680 points

    Hi Mircea

    When the Virtex-4 FPGA is first powered up and before it is configured, the I/O cells are either high impedance (if HSWAPEN = 1) or have weak pull-up resistors enabled (if HSWAPEN = 0). These weak pull-up resistors, in combination with the small (0.1V) voltage difference between the FPGA and ADC supplies make it OK to have this power up sequence.

    What needs to be avoided is having a device with a strong output drive be powered up and driving the ADC inputs before the ADC is powered up.

    I would recommend that the ADC Vdr bus be powered from the same regulator as the Va bus. This ensures these always rise and fall at the same time. I would power up the FPGA and ADC at approximately the same time, or with the FPGA slightly earlier, and have the front end circuitry power up last.

    Once the entire system is powered up, the clock to the ADC is stable and the ADC is configured as desired, make sure that the ADC CAL pin or bit is toggled to re-calibrate the ADC. Please refer to the datasheet for more detailed recommendations regarding calibration.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Intellectual 370 points

    Hi Jim,

    Tank you very much for your quick answer.

    I made logic to start a power rail only after the previous rail (or rails) got to 80% of full level. (this is a requirement for my Altera Arria V device).

    So, I will go with the following sequence (one rail will start after the previous rail reaches 80%):

    1. FPGA core

    2. Other FPGA specific voltages

    3. FPGA IO voltages, 2.5V and  1.8V

    4. ADC 1.9V for Va and Vdr

    5. Power for the Front End and for the PLL generating the 1.500 clock.


    Is that what you are suggesting?


    Thanks,

    Mircea

  • 0 in reply to Mircea Bogdan
    TI__Mastermind 44680 points

    Hi Mircea

    That start-up sequence sounds good to me.

    Best regards,

    Jim B

  • 0 in reply to Mircea Bogdan
    Intellectual 370 points
    Thank you very much.
    Best regards,
    Mircea