DAC3151

Hi,

Are you using the reset pin to apply a reset to this device after power up and before you do any configuration?  if not, then the register space might power up with a strange configuration.

After reset, are you supplying the SYNC signal with the sample data, as well we the ALIGN signal?  Looking at the default values for the register space, the device needs to see SYNC and ALIGN.  If you supply SYNC only, then the synconly_ena must be set by way of SPI interface.  If you are not supplying SYNC, then the sif_sync_ena must be set by way of SPI, and the sif_sync set to 0 and then set to 1.

Otherwise the default register settings should be suitable for basic operation I believe.

Regards,

Richard P.

(I deleted the duplicate posting you had appended to a different posting thread in favor of keeping this posting.)

Thank you for your answer. But I tried it again today,see the Table 17 of the DAC3151 datasheet.I set the bit 11 (fuse_sleep) high,then it can work.But the default value is 0.I would like to ask whether such an operation meet specifications.

Regards

Hi,

you do not have to turn on the fuse-sleep (config10 bit11) to get the DAC to work.  I looked at the default value for config10 and see the fuse-sleep bit is default 0, and I looked at the configuration file that we use with the DAC3151 EVM and the configuration file has the default value ( F080) for config10.  I never touch that register bit.  

when you write to config10 to set the fuse_sleep, what do you put in the rest of the register when you do that write?  Are you using the SPI GUI for the EVM that came with the EVM?  if so, I believe there is a configuration file that comes with the SPI GUI and that file either doesn't write to config10 or it writes the default value to config10.  I just checked, and yes the EVM SPI GUI configuration file does set default values for config10.

usually when I see no output, it is the FIFO that is not reset properly.  The hardware reset pin resets the SPI register space to its default values.  This is necessary, but it does not reset the read and write pointers of the FIFO.  The FIFO is by default enabled, and then the address pointers for the write side needs to be initialized and the address pointers for the read side need to be initialized.  The SYNC input will reset the write pointers.  the ALIGN input will initialize the read pointers.  If you do not provide an ALIGN signal then there is a SPI register bit for sync_only.  This lets the SYNC input reset both address pointers.  If you also do not provide a SYNC signal then there is another SPI register bit that lets you use SPI writes to initialize the address pointers - set sif_sync_ena to a '1' and sif_sync to '0' and then on the next SPI write set sif_sync to '1'.  This makes a software 0 => 1 transition to initialize the two FIFO address pointers.  This is described in the data sheet as Normal dual SYNC, SYNC only, and SIF_SYNC.  section 7.4.1.

There is a mode that the device powers up in after a reset pulse on the reset pin, and from the default values it looks to be Normal dual SYNC, requiring the SYNC and ALIGN signals.  I don't see from the posting if you are using the EVM into the TSW1400 or if this is on your design with an FPGA or something similar.

Regards,

RIchard P.