ADC12J2700 -- can support variable type clock as devclk+/-

HI David,

ADC12D1600 has LVDS interface so it can work with variable clock source range. But ADC12J2700 is a JESD204B part and if you change the clock frequency you will have re-establish the link between the FPGA and ADC.

Regards,
Neeraj Gill

Hi Neeraj,

I appreciate your reply, but I still have more question relation between devclk and sysref.
Our clock input is being changed 270MHz to 450Mhz during one sweep time(like 10us).
It is changed continuously, not setting based.

In this case, do you think I am able to use ADC12J2700 device?
If yes, what about relation between devclk and sysref?
According to 7.3.7.2.9 SYSREF, sysref is defined at 10MHz and 300MHz.
How do I provide sysref clock? Can I use devclk too?

Thanks

Hi David

It is doubtful that the FPGA JESD204B capture hardware and IP can tolerate a ramp in serial bit rate that is that fast. The JESD204B serial data interface is intended for fixed rates and uses PLLs in the capture blocks for clock regeneration.

The even bigger issue is that the ADC12Jxx00 family devices have a minimum clock frequency of 1 GHz.

For this application a better choice would be the ADC12D500RF. This device uses an LVDS interface and can handle modulation of the sample clock frequency. The only requirement is that the effective duty cycle (low period to high period ratio) of the input clock must be within the datasheet requirements (20 to 80 percent) as the frequency is ramped. This device uses a self-calibrated architecture. After power-up and temperature stabilization the device must be calibrated to achieve rated performance. When used in this variable clock application we recommend doing the ADC calibration process at the midpoint frequency to achieve best overall performance over the frequency range.

The LVDS interface of this device should allow the FPGA data receivers to handle the rapid ramp in the Data and DCLK frequency but we have not validated this. I would contact your FPGA vendor to ask about this aspect of the system design.

Best regards,

Jim B

Hi Jim,

It is very good for technical view. Even I implemented with  ADC12D500RF (variable clock mode), I think I could expect to face non-linearity issue during data processing. In order to avoid non-linearity problem, I am considering to normalize(or resample) input variable clock.

What if I am sending fixed clock(450MHz or 1GHz) to capture input data(correlated variable clock like250MHz to 450MHz), what is optimal sampling rate for our application to keep linearity and chipset?

To normalize variable clock, do you have solution chipset or tutorial?

Thanks

Hi David

I don't know enough about your application to know whether normalizing or resampling the ADC output data will provide what you need. Running the ADC at a fixed clock frequency will definitely make the ADC performance more consistent, and will make the data capture job easier.

You could a product like the ADC12J2700, operating at 2700MSPS. This would give 10x oversampling at your original minimum clock frequency of 270 MHz, and 6x oversampling at your max clock frequency of 450 MHz.

The ADC12J2700 datasheet and ADC12J2700EVM documentation are both good references when starting a design using this product. I don't have any specific information on normalizing a variable clock.

Best regards,

Jim B