ADS5281 EVM - how to enable test mode by SPI control software?

Hi,

If you are using the ADS5281 EVM then did you get the TI ADC SPI Interface GUI on a memory stick or CD when you bought the EVM?  That is the SPI GUI that is available for that EVM to connect to the EVM and let you control the SPI registers from the GUI panel on a Windows PC.  The SPI GUI installer is also available on the TI web, but I don't see a link to it at the moment.  The search term I think needs to be very specific to find it.  If you do not have the installer or cannot find it, I can put the installer in a dropbox location for you.

be forewarned though that the SPI GUI Installer is an older piece of software and was made for Windows XP.  A Windows7 PC will fail to find the USB connection to the EVM, but there are instructions on this E2E forum to work around that issue and make the GUI work on a Windows7 machine.  I have the GUI running on my Windows7 laptop.

Whether you use the SPI GUI or some other way to write to the SPI registers (some of our other EVMs would bring the SPI lines to the Samtec connector so the FPGA could drive the SPI but this EVM did not do that.) then you will find a number of registers in the SPI register space to enable test patterns for debugging the serialized data interface.

SPI address 0x25 can be used to enable a custom pattern on the data.  I like to use this to successively try 12 different custom patterns that I have loaded into addresses 0x25 and 0x26.  I would start with pattern 0000 0000 0001 and see if I can deserialize that single bit into the lsb position.  Then I would try 0000 0000 0010, etc, until I walked that single bit up to the msb position in 1000 0000 0000.  this helps get the deserialization logic debugged so that the bits go to the right locations. 

But the walking 1 in the custom pattern doesn't help if you have bits deserialized in the right position but the wrong time.  Like if you get half of one sample put together with half of the next sample.  The 'ramp' pattern enabledin address 0x25 is good for that.  The ramp pattern is another name for an arithmetic counting pattern.  So you can see an output sample of 0x001 followed by 0x002 followed by 0x003, etc, all the way up to sample of value 0xFFF and then followed by 0x000 again as the counter wraps around.  If you can deserialize the ramp pattern correctly, then you've gotten your interface working.

Regards,

Richard P.

Thanks, Richard.

There is no any CD or a memory stick in ADS EVM shipping box.

I could find the SPI installer (ver. SPI 5.1)at the following link:

I have some more questions on SPI software.

1) If there is a manual for SPI software, please let me know how to get it.

2) To use test pattern, do I fill the blanks of Address and Data with Hexadecimal values?

For example, to enable "ramp"  test pattern, is it right step that first fill the address and data blanks with 0x25 and 0x0040 and then press send data?

3) What's the role of 'Test Mode: None' button on SPI software?

And now I will get a new ADS5281 EVM.

I'd like to make sure some procedures to avoid repeted failure to control ADS5281.
Here is a test setup list. Could you give some comments if there are something wrong?

1. Power up ADC EVM with 5 V supply and its ground.
2. Connect the EVM to desktop (Win 7, 64 bit)
3. Install driver (D2XX from FTDI) and SPI software
4. Reset ADC EVM and enable on test pattern (like ramp) via SPI software
5. Feed ADC input clock (50MHz) from FPGA (Virtex5 SX95T) to ADC EVM
7. Capture deserialized ADC signals (bit & frame clocks, data) on chipscope


It would be great to get SPI 5p2 software installer and verilog code for ADC interface as a reference.
My email is smeekim@kaeri.re.kr.

Best regards,

Soo Mee.

Hi,

There is no user guide for the TI ADC SPI Interface GUI, but rather each EVM has a User Guide that includes a section on the use of the GUI tab for that EVM.  The User Guide for the ADS5281 EVM may be found at    You may notice that the screenshots for the GUI reflect something older than the GUI version 5.1 as there had been more tabs added to the GUI for newer devices since the time of the EVM User Guide.  

I have put a zip file of the installer for the version 5.2 SPI GUI at the following dropbox link:

  (This will still have the same issue with installing on a Windows 7 machine - but it can be made to work as previously mentioned.)

Most of the buttons on the SPI GUI should be self-explanatory.  For example, if you click on the test mode control and use it to select Ramp, then you should also see in the ADC SPI History window in the upper right a log of the SPI writes that you have done and you should see a write to an address with the data value needed to enable the ramp test pattern.  Not all of the SPI registers you might want to use will be in the SPI GUI - the GUI was meant to have buttons for the most frequently used features.  But you can still get to any address with any value by using the Address field and Data field followed by Send Data.    (You don't need to use Send Data if you are clicking on one of the controls that *does* map to something in the register map, such as enabling the ramp feature.  Just for address/data pairs would you need to use send data.)  The address and data fields are by default in hexadecimal as seen by the gray 'x' on the left of the control.  But you can use you mouse to change this to decimal or binary or octal if you prefer.

Regards,

Richard P.

Thanks a lot, Richard.

Could you send the zip of ver. 5.2 installer via email (smeekim@kaeri.re.kr)?

Because it doesn't open on explorer of my desktop.

Best regards,

Soo Mee

If I use the 'reset' button on SPI software, I saw in the ADC SPI History window that the command 'reset' sets address, 0x42 with data of 0x8001.

I think the data 0x8001 makes ADS have a differential clock and changes ddr phase with '00' mode.

If I want to use ddr phase '11' mode, is it right to set the address 0x42 with 0x8061?

And after reset and sync pattern by SPI, I captured ADS clocks (fclk and dclk) and samples (data) at the posedge of 2 times bit clock.

I'm wondering why I got the frame clock having not 50% duty cycle or fluctuating in half cycle as shown in attached figure when I changed ddr phase.

If you know the reason, please let me know.

Thanks,

Soo Mee.