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ads804 Schematic check and questions about noise on the ADS input

Florian Berenbrinker
Intellectual 1140 points
Other Parts Discussed in Thread: ADS804

HI E2E,

 

I am using and ADS804 for some DYI project.

 

I got the sampling working but I see strange noise (around 10mV p to p) on my input into the ADS804 in.

I use the singled ended swinging input generated cm by a voltage divider of REFB and REFT.

 

I have attached the ads schematic and the input filter schematic to this post.

 

Do I miss to place 100nF caps on REFB and REFT?

Do I miss to place 100nF caps on +/-5V of the Opamp VCC supply?

 

My +/-5V supply VCC has an ripple form about 80mV p to p.

The 3.3V ads supply has an ripple around 25 mV p to p.

 

My ADC clock is 2Mhz derived from the PLL of an FPGA.

 

Thanks for your help

Regards Florian

  • 0
    TI__Mastermind 29220 points

    Hi,

    May i see a scope screenshot of this noise that you see on your input signal?  If you see this noise at the input pins of the analog signal or nearby thay location, then i suspect you sre simply seeing the sampling glitches that are kicked back onto the analog input by the ADC input track and hold circuit.  Do an internet search on samplign glitches or track and hold circuits to see what i mean.  The front end of an ADC has a track and hold circuit such that during the clock low time the input circuit has a sampling capacitor that is tracking the input voltage.  When the clock goes high, then a switch opens that isolates the sampling cap from the input so that the analog input is 'frozen' on the sampling cap and the ADC has time to resolve that analog voltage into digital bits whils the clock is high.  This opening and closing of the switch to isolate the sampling cap or not causes noise to be kicked back onto your input voltage.  As long as the noise settles out before the next clock rising edge and doesnt affect the next sampling instant then there is no harm done.  Or if the ADC can integrate a nice linear isolation buffer on silicon to isolate the track and hold from the external world then you would not see the sampling glitches.  But these older devices usually do not have such an isolation buffer.

    Look at your noise on the scope and see if the occurrence if these noises happen with clock rising and falling edges, that would be further confirmation that you are seeing sampling glitches.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    TI__Intellectual 1140 points

    Hi Richard,

     

    thanks allot for your answer. I think you are correct I see the kickback of the ADC internal CAP.

     

    As you mention I did 3 different measurements.

     

    1. ADC Is driven by 2MHz clock. I can see that my noise is the same as my ADC clock. The high ripple seems to be coupling in the oscilloscope probe.
    2. ADC Is driven by 2MHz clock. I only measured the noise on the R3_A resistor.
    3. No ADC clock running on VCC supply active.

     

    But it’s hard to me to judge if these kickback is OK or not. Perhaps you can do that.

     

    Thanks & Regards

    Florian