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GSPS product configuration for mmWave applications

Other Parts Discussed in Thread: TIDA-00467, LMK04828, DAC38J84


I am building a mmWave system evaluation platform. I will be using V|E-band transceivers with analog BB/IF differential IQ ports interfacing the DAC/ADC boards. In order to generate and capture 1 to 2 GHz bandwidth signals (i.e. from Matlab in the early project stages) I was planning to use the following TI evaluation boards configuration: 

-  1x TSW14J56EVM + 1x DAC38J84EVM (The I and Q TX paths share a multi-channel multi-GSPS DAC solution)

-  2x TSW14J56EVM + 2x ADC12J4000EVM (Each I and Q RX path includes a single-channel multi-GSPS ADC solution, since I am not aware that there is any TI FMC multi-channel multi-GSPS ADC solution compatible with the TSW_EVM pattern generation/data capture boards).

Since it is important for the I and Q RX paths to be properly synchronized and triggered I was thinking of using the configuration shown in the High Speed TI design “Synchronizing Multiple JESD204B Analog to Digital Converters for Emitter Position Location” (ACTIVE TIDA-00467).  

Will the previous synchronization configuration work for GHz-bandwidth RX signals like those used in mmWave communications?

Thank you very much for your help and BR.

  • Hi David

    For the ADC portion of the system, the method of TIDA-00467 will work for sampling rates up to 3.072 GSPS (the maximum rated frequency of the LMK04828). 

    One of my colleagues will respond regarding the possibilities of synchronizing the DAC system to this dual ADC system.

    Best regards,

    Jim B 

  • Hi David,

    The DAC38J84 is JESD204B subclass 1 device and can achieve multiple DAC38J84 device synchronization in terms of digital latency as well. 

    Here is a E2E link to some discussion that we had on implementing this on Xilinx FPGA platform with two DAC38J84 EVMs

    Please note that all the multiple device synchronization for both ADCs and DACs can only help achieve synchronization in terms of digital latency (i.e. from ADC to FPGA and FPGA to DAC). In terms of achieving synchronization on the analog input and output, additional work on your side will be needed. For instance, you may need to take care of external analog interface network to ensure both I and Q input/output of ADC and DAC have equal group delay. In terms of baseband processing, you will need to create some sort of frequency compensation coding to take care of frequency offset from doppler shifts and multipath effect. These analog delay will not be part of the JESD204B synchronization. 


  • Hi Jim,
    good! Thanks for your answer.
  • Hi Kang,
    indeed I was interested in the digital latency issues but thank you also for the analog/ota domain synchronization recommendations.