On the ADS5560 data sheet, the block diagram shows a sample and hold block, which is implemented with FETs and Capacitors as shown on figure 45. The sampling switch must go to Ron=10 ohms for a while to sample the differential voltage on to the capacitors, then shut off to hold the charge. The RC time constant for half of the differential sample circuit is ~20 ohm * 6 pF = 120 ps, so the sampling switch must be on for at least 4*RC = 500 ps. The aperture spec tA in section 6.11 is 0.5-2 ns, from the rising clock edge. Does this mean that the sampling window opens up 0.5-2 ns after the clock edge, and then closes some time later, or that the sampling window closes 0.5-2 ns from the rising clock edge, and opens sometime earlier? Or maybe it opens and closes, centered around 0.5-2 ns after the rising clock edge? How do we know how long the sampling switches are turned on?
I need to put an analog multiplexer in front of the ADC differential inputs to switch input sources, and I need to know how soon after the rising clock edge I can safely switch the input source, and how quickly the ADC inputs need to be ready for the next measurement. (The hold and setup times for the analog inputs, with respect to the rising edge of the clock.) The clock period of the ADS5560 is 25 ns.
