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SPI (?) of ADS8353, ADS7853, ADS7253

Michele Citterio
Prodigy 40 points
Other Parts Discussed in Thread: ADS8353, ADS7853, ADS7253, SN74LVC2G74

Hi,

Can someone confirm that the ADS8353, ADS7853, ADS7253 do indeed have SPI as stated in the product page but nowhere in the datasheet? I mean, 'real' SPI. And if they do, what SPI mode exactly?

I may be too tired right now but the lower panel of fig. 1 in the datasheet (SBAS584B –OCTOBER 2013–REVISED AUGUST 2014) and also the specification of a Max(t_D_CKDO) don't look like SPI to me. Is the next bit really clocked out max. 20 ns after the SAME (falling) edge marking the sampling of the current bit, instead of after some setup time after the immediately following rising edge? If so (which is not SPI) what is relevant is the unspecified MINIMUM t_D_CKDO so that I can make sure the minimum input hold time of the master is satisfied.

On the other hand the top right panel suggest it is CPOL=1 CPHA=1, so mode 3, which would be good old SPI mode 3. These things will end up in the Arctic and I'm too much in a hurry to find out later on that the output timing of these devices are so to speak a little funny. Sure I could latch the MISO myself - I just need to know for sure that it is actually needed...

Many thanks from Denmark,

Michele

  • 0
    TI__Guru 52796 points

    Hello Michele,

    As you mention, per the datasheet timing spec, the serial interface of the ADSxx53 family updates the SDO data on the falling edge of SCLK; and also latches SDI data on the falling edge of SCLK.  This is different than conventional SPI CPOL/CPHA settings, where SDO is updated in one SCLK edge, and SDI is read on the opposite SCLK edge.  In many applications, this device is interfaced with FPGAs or controllers that provide the option to control the timing/edges to capture or latch data.

    You are correct, if you require to interface with a controller supporting the SPI mode CPOL/CPHA settings, one option is to add a positive-edge–triggered D-type FLIP-FLOP (SN74LVC2G74) at the SDO output as shown below.  When using this D Flip-Flop circuit, this allows the user to support both the READ/WRITE transactions data from the device using in CPOL=0, CPHA=1.  I will follow–up with the team to update this information on the webpage.

     

    Thank you and Best Regards,

    Luis

  • 0 in reply to Luis Chioye
    Prodigy 40 points
    Thank you Luis, it's a big selling point that TI offers this kind of fast and thorough support. Best regards, Michele