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DAC714 control

Other Parts Discussed in Thread: DAC714

hello,

I use the DAC714 for my new project. my question is simple, do I need use the CRL pin to clear the registers before each conversion cycle.
I shift my data in the shift register, latch it with the A1 control pins, all is ok. But for a next conversion cycle, the result is not coherent, it seems that the data are correctly shifting on the first register, but when I latch on the second register, the bait placed during the first conversation stay on its highest level, if I don't make analyses errors.
Do I need to clear the data on the DAC714 before each conversion?
ps: sorry if I made language

regards

Hocine BELHAOUES.

  • Hi Hocine,

    Hocine Belhaoues said:
    Do I need to clear the data on the DAC714 before each conversion?

    No. You should not have the clear the device before every communication cycle.

    Hocine Belhaoues said:
    I shift my data in the shift register, latch it with the A1 control pins, all is ok. But for a next conversion cycle, the result is not coherent, it seems that the data are correctly shifting on the first register, but when I latch on the second register, the bait placed during the first conversation stay on its highest level, if I don't make analyses errors.

    Can you share an oscilloscope capture of the digital interface during these transactions? I would like to verify that all the timings are correct.

    What voltages are you using for the supplies?

  • it is the fonction wich command the DAC,

    The clock is simulated by the pin portC3 by a clock with a period of 200us.

    the voltage for the supplies is 5-0V


    {
    int i;
    LATB.LATB4 = 1; // Ao
    LATB.LATB5 = 1; // A1
    LATC.LATC3 = 0; // CLK
    LATB.LATB4 = 0;
    for (i=0; i < 16; i++)
    {
    delay_us(100);
    LATC.LATC3 = 0;
    delay_us(100);
    if ( tab[i] == '1' ) //
    LATC.LATC5 = 1; // Recup the data on portC5 pin
    else if (tab[i] == '0') //
    LATC.LATC5 = 0; //
    delay_us(100);
    LATC.LATC3 = 1;
    }
    LATB.LATB4 = 1;
    delay_us(100);
    LATC.LATC3 = 0;

    LATB.LATB5 = 0;
    delay_us(100);
    LATC.LATC3 = 1;
    delay_us(100);
    LATC.LATC3 = 0;
    LATB.LATB5 = 1;
    }

  • Hi Hocine,

    Apologies, the resolution of the picture makes it impossible for me to read the schematic. Also, it will be necessary for me to get a capture of both digital transactions occurring in order to give you a good review of interface. This is because there could be problems happening when the output toggles.