ADS8519 - ADC - Sampling Rate_Question

Hello Jose,

Thanks for your reply. As per the data sheet, I am making the Ext/Int# signal always low, and trying out internal clock mode. CS# is always tied low as well. I am using R/C# signal,and currently using it at 50ns minimum timing.(page 7/28). Should I reduce R/C# to say 30 ns, to achieve lower sampling rate around 125KSPS?.

Attaching the datasheet for your reference.

Thanks,

ManojADC_ADS8519.pdf

Thank you Jose.

So, I understand that when Ext/Int is set to Zero. The ADC goes into internal clock mode. We are using a function generator to feed input to the ADC and are checking the output through an oscilloscope.

Lets say, if I monitor data and clock pin simultaneously. For 16 clock pulses, I am getting a valid data output. Does the MSB of the data corresponds to sign bit?.........

Hello Jose,

As per our conversation, lets say if I toggle R/C every 8 us, what will be timing of  t conv(conversion time) and t acq(acquisition) time.

On the whole, how will figure 2 (Basic conversion timing: internal data clock) look like?.

Thanks,

Manoj

Thank you Jose. That helps

Hello Jose,

We tweaked the timing as per our discussion, and toggled R/C low for every 8us to achieve  125KSPS sampling rate, but, the issue here is that, the acquisition time increases and hence the overall cycle time (t_conversion + t_acquisition) increases above 4us( which exceeds the maximum timing requirements as per page 7).

Wouldn't this cause an issue with the chip's functionality ?

Regards,

Manoj