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ADS556x LVDS bits 14/15 to J10 not shown on the schematic

David Forey
Prodigy 20 points
Other Parts Discussed in Thread: ADS5560, ADS6149, FMC-ADC-ADAPTER, ADS5560EVM

ADS61x9/55xxEVM User's Guide (June 2009) does not show the connections from the ADS5560 (16-bit ADC) to the J10 connector.  The schematic shows for instance, that 'D0_D1' is connected to J10-82 but on the schematic for the FMC (http://focus.ti.com/docs/toolsw/folders/print/fmc-adc-adapter.html) J10-82 is 'IO_10N'.  The ADS5560 schematic also does not show the higher order bits.  Only 14 bits are shown even though it is a 16 bit ADC.

  • 0
    TI__Guru 72529 points

    Hello David,

    I apologize for the confusion. The schematic symbol for U1 was the ADS6149 family, which is a 14bit ADC. The pinout of the LSB driver starts from pin 33.

    The EVM can also accomodate the ADS5560, which is a 16-bit ADC. The LSB pins of D0_D1_p and D0_D1_m start at pin31 and pin 32, which are labeled as "RESERVED-P" and "RESERVED-M" The MSB pins of D14_D15_P/M at pin 47 and 48 are labeled as D12-D13_p/m, respectively. 

    The labeling does not affect the EVM operation. The connections to the connector J10 are correct, and connector J10 will see all 16 bits of data. 

    Hope this helps.

    -Kang Hsia

  • 0 in reply to Kang Hsia
    Prodigy 20 points

    Thanks, that does help.

    Is there also a notation error in the routing to the EVM-J10 connector?  If you trace "RESERVED_P" to EVM-J10-pin88, it then connects to "IO_11N" of TI's "FMC-ADC-ADAPTER".  The P/N swap is consistant for all bits.  Xilinx ISE produces an error regarding the differential pair locations.  The error is resolved by swapping the P/N for each bit.

  • 0 in reply to David Forey
    TI__Guru 72529 points

    Hi David,

    In order to accommodate all of our TI high speed ADCs, we had to make the FMC-ADC-adapter as generic as possible. The notation of the P/N on the FMC-ADC-adapter matches most of our ADCs (i.e. ADS62Pxx family) but not the ADS5560 family. When designing our EVMs, our priority is to make an EVM that will demonstrate the best performance of our ADC. 

    The schematic for the ADS5560 and ADS61xx EVM was drawn such that the physical layout of the LVDS P and N pair will not cross when routing from the chip to the J10 connector. This is the best way to maintain the signal integrity of the LVDS pairs. This also works out because the polarity of the LVDS data can be changed in the FPGA firmware. 

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 70 points

    I also have the ADS5560EVM and I am trying to access the digital output on connector J5 but it seems that bits 14/15 are not routed to this connector. Is this correct? If so, how can I obtain the 16-bit single-ended output?

  • 0 in reply to Neema Daneshvar
    TI__Guru 72529 points

    Hello Neema,

    The ADS5560 EVM shares the same EVM as the ADS61x9 ADC family, which are 14-bits and higher speed. We have overlooked the 2 extra bits needed for the 16-bit ADS5560 family. Therefore, we are currently revising the EVM to accommodate for the 16-bit CMOS output. We will finish the redesign in a week and release to fab to testing.

    In the mean time, we have a adapter board available for you to externally route out the CMOS output to a header. We will be happy to ship this adapter board to you for your evaluation. See attached for the schematic of the adapter board. 

    Please provide your contact infromation so we can exchange shipping information offline. Thanks.

    -KH

    BreakoutBoard_A-sch.pdf
  • 0 in reply to Kang Hsia
    Prodigy 70 points

    Hi Kang,

     

    Please email me at neema@silvustechnologies.com

     

    Thanks,
    Neema 

  • 0 in reply to Kang Hsia
    Prodigy 80 points

    Hello Kang,

    I came across this posting after searching for information regarding the ADS5560EVM using its CMOS output mode.  I  need to design an interface to the EMV for this CMOS data output, but the schematic supplied from User's Guide SLAU260-December 2008 only shows 14-bits available on output connector J5.  Your post on Apr 15, 2011 indicated that you are currently revising the EVM to accommodate for the 16-bit CMOS output.  Will you please send me the corrected schematic for this new EVM board?  Is there a revised User's Guide available, and if so will you also send that to me? Contact info is jim@cybertro.com.

    Thank you,

    Jim Brennan

  • 0 in reply to Jim Brennan
    TI__Guru 72529 points

    Hello,

    Please refer to the following post for updated revision C schematic.

    http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/p/104917/1037557.aspx#1037557

    -Kang