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Some software questions about the ADS1248

Wayne Radochonski
Prodigy 90 points
Other Parts Discussed in Thread: ADS1248, ADS1278

I'm working on a wave energy project that requires digitzing the following sensors (all at 10 Hz,  50 samples/sec in aggregate):

-- Two  type T thermocouples converting -20 to +100 Celsius, ADS1248's internal diode will be used as the "cold junction".  Software will perform the cold junction compensation.

-- One three wire RTD, converting -20 to +100 Celsius

--  Two pressure sensors that produce 0 to 10 volts

The ARM microcontroller that I'm using is limited to 8 to 16 bit transfer on its SPI interface.  Of course, given my slow sampling rate of 10 Hz it is possible to "bit bang" the SPI interface to get achieve 24 bit transfers or gain more control over the ADS1248 signal timing.

To read the five sensors listed above, I think the software must do something like the following:

1.  Pulse -RESET to initialize the ADS1278

2. Assert START to start or continue conversions (Must START be asserted to access the configuration registers?)

3.  Configure the ADS1248 using the Register Write and Register Read commands.  (Can all of the registers in the ADS1248 be read as well as written?)  -CS is asserted during the configuration to select the ADS1248.

4. Wait (for an interrupt) on the assertion (falling edge) of -DRDY

5. Issue 24 SPI clock pulses, result of previous conversion appears on DOUT, MSB first.  Select the next channel to be converted, by writing the MUX0 register using the WREG command on DIN.  Twenty four bits in and out on the DIN and DOUT.

Steps 4 and 5 are repeated as long as START is asserted.

If I want to achieve a 10 Hz sampling for 5 sensors, I should specify 80 Hz in DOR[3:0] of SYS0.  Three unwanted sensor inputs can just be discarded.  80 Hz / 8 sensors should give me a 10 Hz sampling rate.

Here are some questions about the software interface:

Since my CPU can only transfer 8 or 16 bits on the SPI interface, can the ADS1248 tolerate a non continuous SPI clock?  If I break a 24 bit transfer into three 8 bit transfers, the SPI clock will stop and -CS will negate between transfers but the duration will be short, probably less than 1 uS.  One of the responses in the forum suggested that negation of -CS during a transfer doesn't bollux DOUT but resets DIN. Perhaps, I need to "bit bang" -CS so that I can actually perform step #5 above.

Page 55 of the ADS1248 data sheet claims that READC is the default behavior of the ADS1248.  When would the READ, READC and SYNC commands be used?

Thanks for your help,

Wayne

  • 0
    TI__Guru* 98335 points

    Wayne,


    I'll just comment on loosely following your points, in the order that I think things should happen. Then I'll address the questions.

    1. I would power things on with START high. If START is low, or if it is taken low for a long time, it may power off the ADS1248. By powering on the device with START high, you make sure the part is on and ready to take input.

    2. Then I would pulse the RESETn to make sure everything is in the proper state.

    3. The next command I would do is SDATAC because RDATAC is default. If you're going to be talking to the ADS1248 you want the communications to be uninterrupted. With RDATAC the DOUT will be updated each time the DRDYn is indicated. Imagine if you're in the process of reading the register, and in the middle of that, the DOUT is updated with the new data.

    4. Configure the ADS1248 with WREG. After that you can perform the RREG and read all the registers back at any time.

    5. At this point, the part is still converting, but not putting any data out to DOUT. You can do several things, depending on how you want to use the part and get data. You can read data once by RDATA, or multiple times with RDATAC. You can synchronize conversions by pulsing the START pin low or by performing a SYNC command.

    6. If reading out data, you can wait until the DRDYn is asserted and clock out the data and then WREG the next configuration into the registers and repeat the method of reading data.

    Here are some answers to the questions.

    The ADS1248 can tolerate a non continuous SPI SCLK, so 8 or 16 bit transfers should not be a problem. However you should keep CSn low for communications with the part until the communication is completed (collecting data is the exception to this). The CSn going high is used as a reset for the SPI communications.

    As mentioned earlier, you use the SDATAC so that DOUT isn't updated with each conversion, and that reading from the register can take place uninterrupted. The RDATA is used to get the next data out and hold it there (even if conversions are still taking place). SYNC is used to time a conversion so that it takes place at a particular time. Imagine SYNC as a reset to the digital filter so that the conversion starts at the last falling pulse of the SCLK for the command.

    If you have any other questions let me know.

     

    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 90 points

    Joseph

    I'm still a bit confused about timing of reading the samples.  Hopefully, I can describe what I want to do clearly.

    I must read 4 sensors at a 10 Hz rate, so I think that I should specify an 40 Hz aggregate sampling rate.  My understanding (probably incorrect) follows:

    1. Issue SREADC to stop conversion, and then WREG to configure the ADS124X and select the first channel.  RREG can be used to verify configuration has been done correctly.

    2. READC, starts the conversion.  Assertion of -DRDY indicates the data is available.

    3. READC, Select the next channel.  Repeat step 3 as long as data is collected

    4. When done, issue SREADC to stop further conversions

    Are the above steps correct?

    Based upon your comments about -CS assertion, I will use a GPIO from the processor and control its assertion and negation in software.  This will insure that -CS is not negated in the middle of a multiple byte transfer of the converted data.  If this idea won't work, please let me know.

    If I'm reading 4 channels at 10 Hz by specifying an 40 Hz sampling rate, each channel requires 25 ms to convert.  Although each sensor is sampled at 10 Hz, there is a 75 ms delay between sampling the first sensor and sampling the last sensor.  This probably not acceptable for our application.  I guess there are two choices for me,  increasing the sampling rate, read four samples at the faster rate, then stop the conversion.  The sampling process can be re-started by a timer interrupt.

    Another approach would be to use four ADS1246s (three for the thermocouples, one for the RTD), each set to sample at 10 Hz.  The START signal or SYNC command can be sent to all of the converters to synchronize their conversions; all four can be read when -DRDY is asserted (falling edge).

    Is -DRDY open drain?  I looked through the data sheet quite closely but could not find any indication of the driver type fpr the outputs.  I know DOUT is tri-state since there is a timing diagram that specifies the time from negation of -CS to DOUT floating.

    Any other considerations to be aware of when operating multiple ADS1246s?

    Thanks again for your help.

    Wayne

     

  • 0 in reply to Wayne Radochonski
    TI__Guru* 98335 points

    Wayne,

    First just to clear one thing up, if you do not need to read back the device, you don't need to do a SDATAC. In this case DOUT would only be used for reading data. Also, you can set the configuration at the same time you are reading data. As you are clocking in the configuration register, the data is being clocked out on DOUT.

    Figure 80 shows the power-up, configuration setup, read out of data while setting the next configuration. You could run this at 40Hz and get 4 data reads but you have a delay based on the amount of time it takes to read data and set the configuration. If you absolutely need 10Hz read out and can't tolerate and extra ms of time, then I'd go faster and suffer the slight noise penalty. Read through the figure, it might be what you want to do.

    As for your description, RDATAC does not start a conversion, it only allows data to go to DOUT when the DRDYn is indicated. Setting the multiplexer (or anything in the configuration), issuing a SYNC command, or pulsing the START pin low will start a conversion (clearing the digital filter so the data will be good).

    I'd say it this way if you need to read back the configuration register and you run the part at a data rate of 40Hz and can tolerate a small amount of extra time:

    1. SDATAC, WREG for config, RREG to check the write
    2. RDATA, wait for DRDYn, clock out data, WREG for config, RREG to check the write
    3. Repeat 2 as necessary

    If you don't need to check the write then do this:
    1. WREG for config, wait for DRDYn, WREG for config and clock out data at the same time.
    2. Repeat 1 as necessary.

    If you can't tolerate the extra time, you'll need to run it at 80Hz and initiate the conversion at the change of the MUX.

    Here are a few answers to other comments.

    Using the GPIO from the processor to control the CSn line should work. I'm not sure if we've used it for this in our EVMs, but I don't forsee this as a problem

    If you are using four devices, it generally isn't going to be a problem. However if you use the internal clock for all of them, then the devices will complete conversions at different times, If the master clock is shared by all devices, this won't be a problem.

    DRDY is not open drain. It uses standard CMOS logic levels.

    If you have any other questions let me know - you can post to this thread again.


    Joseph Wu