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1MHz external clock on ADS1246/7/8

gopimn
Prodigy 30 points
Other Parts Discussed in Thread: ADS1247

Hello!

I'm working with the ads1247 and I would like to know what are the consequences on the samples per second with an external clock of 1MHz.

A previous post talks about the lower external clock consequence on the SPI clock,  with a recommendation that V_{refex}=2xSPI_{clock} :

https://e2e.ti.com/support/data_converters/precision_data_converters/f/73/t/369305

The datasheet has some tables with a 4 MHz clock and there's  ~ 0.5 ms between samples, what is the expected value for a lower clock?

Thanks in advance.

My regards,

___

FMN

  • 0
    TI__Guru* 94285 points
    FMN,


    If you're asking about the data rate and the timing information, then all timing scales with the external clock. With an external clock at 1MHz, and the nominal clock at 4.096MHz, the timing gets more than 4x longer.

    For the data rate, it becomes more than 4x slower. As an example if the data rate is set to 2kSPS, then the new data rate with the 1MHz clock becomes 488Hz.

    Did you have a more specific question about a particular table? Or did this answer your question?


    Joseph Wu
  • 0 in reply to Joseph Wu
    Prodigy 30 points

    Dear Mr Wu,


    Thanks for the answer, actually I tested it with a signal generator, and the conversion time (the time that takes DTRDY to go low) changed according to the clock frequency. There's something though, when the clock is less than 2MHz the conversion time is not constant, if you want I can send you the screenshots.

    Now well, do you know which is the current needed by the clock pulse in order to be correctly readed by the ADC?

    Thanks Again,

    ____

    FMN

  • 0 in reply to gopimn
    Prodigy 30 points
    The datasheet talks about a input leakage current of 10 uA, is that it?
  • 0 in reply to gopimn
    TI__Guru* 94285 points
    FMN,


    Go ahead and send me the screen shots. I'd like to see the issue you're having.

    Thinking about it, the conversion time should be constant with a constant clock. At 2MHz, it should not have a variable conversion time. When data is taken, there are a set number of clock pulses required to make a conversion and there should be no way to speed up or slow down the conversion except through the clock rate.

    I don't have any information on the current needed by the clock pulse to be correctly seen by the ADC. The input leakage number is given as a metric to show that there may be some input minimum drive needed for the digital drive. I would imagine that you would need much less than this to drive the clock line, but it is a good guess for a maximum.


    Joseph Wu