DAC5681 FIFO_ERR after start-up

Hi Shimizu,

I am looking into this, will reply as soon as I can,

Regards,

Neeraj Gill

Hi Shimizu,

FIFO_ERR is asserted when the FIFO pointers over run each other causing sample to be missed. This error occurs when DACCLK AND DCLK are not properly aligned. The customer should make sure the DACCLK and DCLK are aligned.

If customer cannot align the two clocks properly he may be able use FIFO_offset in config 1.

Please note the default value for FIFO offset is 0, so the customer has to set this register upon each start up.

Regards,

Neeraj Gill

Hi Shimizhu,

Sorry for confusion

What I mean by DACCLK is the CLK signal going into CLKIN/CLKINC pins to drive the DAC.

DCLK is clock signal from your FPGA which is used to CLK data into the DAC.
Signal going into CLKIN and DCLK signal should be synchronized with each other.

Yes aligned means synchronization of DCLK AND CLKIN.

Regards,
Neeraj Gill

Hi Shimizu,

Synchronization of CLKIN and DCLK mean both the clock signals should have constant phase between them.
For example for the DAC5681EVM there is CDCM7005 (clock distribution chip) it takes the external clock and generate CLKIN signal and reference signal for (TSW1400)FPGA. Both CLKIN signal and reference signal for FPGA are synchronized to each other. The FPGA uses the reference signal uses its internal PLL to generate DLCK, so the DCLK is synchronized with CLKIN signal.

Regards,
Neeraj Gill