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DAC5681 FIFO_ERR after start-up

masahiko shimizu
Guru 11235 points
Other Parts Discussed in Thread: DAC5681, DAC5681EVM, CDCM7005

Hi,

My customer is using DAC5681.
He has a isuue at FIFO_ERR after start-up.

He has RECOMMENDED STARTUP SEQUENCE in datasheet.
After this startup, FIFO_ERR is High logic.

Do you know why FIFO_ERR is High logic at this situation?
Could you give me advice for this issue, please?

Best reagrds,
Shimizu

  • 0
    TI__Mastermind 20541 points

    Hi Shimizu,

    I am looking into this, will reply as soon as I can,

    Regards,

    Neeraj Gill

  • 0 in reply to Neeraj Gill
    TI__Mastermind 20541 points

    Hi Shimizu,

    FIFO_ERR is asserted when the FIFO pointers over run each other causing sample to be missed. This error occurs when DACCLK AND DCLK are not properly aligned. The customer should make sure the DACCLK and DCLK are aligned.

    If customer cannot align the two clocks properly he may be able use FIFO_offset in config 1.

    Please note the default value for FIFO offset is 0, so the customer has to set this register upon each start up.

    Regards,

    Neeraj Gill

  • 0 in reply to Neeraj Gill
    Guru 11235 points
    Hi Neeraj,

    Thank you for your support.
    I have some question to your answer.
    Could you answer me the below questions, please?

    Q1: What is DACCLK?
    In datasheet, DACCLK is showed as internal.
    From what clk is DACCLK made? -> DCLK? CLKIN?

    Q2: What does "aligned" mean?
    -> Synchronism of DCLK and CLKIN?

    Best regards,
    Shimizu
  • 0 in reply to masahiko shimizu
    TI__Mastermind 20541 points
    Hi Shimizhu,

    Sorry for confusion

    What I mean by DACCLK is the CLK signal going into CLKIN/CLKINC pins to drive the DAC.

    DCLK is clock signal from your FPGA which is used to CLK data into the DAC.
    Signal going into CLKIN and DCLK signal should be synchronized with each other.

    Yes aligned means synchronization of DCLK AND CLKIN.

    Regards,
    Neeraj Gill
  • 0 in reply to Neeraj Gill
    Guru 11235 points

    Hi Neeraj,

    Thank you for your reply.

    Is there the rule about synchronization of DCLK and CLKIN in datasheet?
    My customer has FIFO_ERR issue at startup.
    I must explain the mechanism to customer.

    I want to indicate to synchronization of DCLK and CLKIN to my customer.

    Could you let me know  the rule about synchronization of DCLK and CLKIN, please?

    Besr regards,
    Shimizu

  • 0 in reply to masahiko shimizu
    Guru 11235 points

    Hi Neeraj,

     How is the progress about this?

    Best regards,

    Shimizu

  • 0 in reply to masahiko shimizu
    TI__Mastermind 20541 points
    Hi Shimizu,

    Synchronization of CLKIN and DCLK mean both the clock signals should have constant phase between them.
    For example for the DAC5681EVM there is CDCM7005 (clock distribution chip) it takes the external clock and generate CLKIN signal and reference signal for (TSW1400)FPGA. Both CLKIN signal and reference signal for FPGA are synchronized to each other. The FPGA uses the reference signal uses its internal PLL to generate DLCK, so the DCLK is synchronized with CLKIN signal.

    Regards,
    Neeraj Gill