ADS5444

Hi,

take a look at figures 24 and 25 in the datasheet.   These figures show how SNR and SFDR begin to degrade as the clock amplitude gets smaller, and from there you can decide for yourself what you would like to set for the minimum clock amplitude.   The performance of SNR and SFDR is relatively flat over clock amplitude until the clock amplitude begins to get down towards 1V peak to peak differential, and below 1V p-p differential the performance really begins to diminish rapidly.    You may choose to take 1.5V p-p differential as your minimum clock amplitude if you don't want to give up anything on SNR and SFDR, for example.

Regards,

Richard P.

Are figures 24/25 based on a sine wave clock input? I'm curious if the performance degradation at lower amplitude is caused by slope dependent jitter. Would a logic driven clock with faster edge rates (Figure 38) exceed the figure 24/25 performance curves at lower amplitude?

Yes, these figures and pretty much all characterization if based on sine wave clock.  In theory, the sharper edge rate of a more square-wave shaped clock would help, but in practice there is no good way to get an apples-to-apples comparison of a sine wave clock compared to square wave clock.   Even the best signal generators that we can buy for the lab for generating the clock will still have significant phase noise, too much to really show the intrinsic performance of the data converter, so we use very narrow-band bandpass filters to remove as much phase noise from the clock as we can.   And the bandpass filter removes harmonics as well leaving a sine wave clock.   Running the clock then through a buffer device to output a square wave adds back in the jitter performance of the active buffer itself.   So sine wave clocks remain the primary condition for device characterization of AC performance.

Regards,

Richard P.