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Low IF Receiver Reference Design

Other Parts Discussed in Thread: LMK04031, LMH6517


We have some preliminary sketches above the block diagram of receiver. 

 I am found some idea  in article:  snau078  "Low IF Receiver Reference Design". I have some questions:

1) In  SP16130CH4RB Reference Board using CVHD-950-100 -> Low Noise Oscillator and LMK04031 -> Clock Jitter Cleaner.

Phase Jitter  [CVHD-950-100]

1kHz            -140 dBc/Hz
10kHz         -155 dBc/Hz
100kHz       -164 dBc/Hz
1MHz           -166 dBc/Hz

VCO Closed Loop Phase Noise  [LMK04031] -> fCLKout = 250 MHz

1kHz            -125 dBc/Hz
10kHz         -130 dBc/Hz
100kHz       -132 dBc/Hz
1MHz           -148 dBc/Hz

CVHD-950-100 has better phase noise performance  than  LMK04031. Why using  Clock Jitter Cleaner with CVHD-950-100  in  SP16130CH4RB board ?

2) Could you recommend me ultra low noise amplifier [block before LMH6517] ? 

I am hope for your understanding and help.


  • Alex,
    1) Yes, you are right that the phase noise of that VCXO is very good, although an appropriate clock frequency must be generated for the ADC (~130MHz in this case) which may not necessarily be available from the CVHD-950 VCXO. This reference design demonstrates using the LMK04031 as a dual PLL reference clock cleaner and frequency synthesizer.
    2) I think an amplifier that could work for you is:

    Regards, Josh