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one question about Eval board ADC08B3000RB

Guo ya
Prodigy 35 points
Other Parts Discussed in Thread: ADC08B3000

      I' m using an Eval board  ADC08B3000RB ; But I donnot know  if we can get high and low digital levelI （LSB-MSB） from expansion header  independently;  for example（high and low digital levelI ）as follows :

       I want to know if we can get connect up with the ADC Eval board expansion header in a way that we can get the LVDS output data onto SMA connectors to connect up to an oscilloscope; In which condition,we can achieve this result.

     

          Best regards,

         guoyacekong@163.com

  • 0
    TI__Mastermind 44570 points

    Hi Guo

    While the ADC08B3000RB hardware includes the expansion header, the FPGA firmware for that EVM does not include support outputting the ADC data on the header.

    Also, since the ADC08B3000 is has a data buffer and CMOS data outputs, the maximum data output rate would be periodic bursts of up to 4k bytes of data limited by the speed of the CMOS interface between the ADC and FPGA.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 35 points

    Hi jim

         Thanks for your  guiding  idea. If  the EVM  does  not  include supprt  outputting the ADC data on the header.  Nevertheless  i  read  "ADC08B3000RB  Reference Board User’s Guide"  information from TI official  website.

    as follows:


    Expansion Header:A 72-pin Future Bus Expansion Header (Table 3)is provided on the rear panel to allow easy connection to a third-party microprocessor board to allow for the reading and analysis of the data captured by the FPGA.

    The Data busses on this header may be configured as follows:


       Dear jim ,My  problems may  be very  simple for  most  people . I hope you don not be angry. I Still cannot understand what  are the expansion header for using.

  • 0 in reply to Guo ya
    TI__Mastermind 44570 points

    Hi Guo

    The expansion connector signals are physically connected to the FPGA outputs, but the FPGA firmware does not have any signals going to those FPGA output pins.

    I was not involved in the design of this board, but I believe the initial plan was to add this feature to the firmware with signal names as listed in Table 3, but that never happened.

    I'm sorry but I don't have more information than what I have already provided.

    Best regards,

    Jim B