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TSW14J10 and TSW12J54EVM: Timeout error after programming via EVM GUI

Other Parts Discussed in Thread: ADC12J4000EVM, TSW12J54EVM, ADC12J4000, LMK04828

I'm in the process of evaluating the ADC12J4000 on the VC707 evaluation board and have decided to use the TSW14J10 to help verify a few operational modes on the ADC. I have followed the setup guide in the TSW12J54EVM product guide, which says to use the ADC12J4000EVM GUI to program the device and HSDC Pro to view the captured data.

After programming the ADC EVM and configuring the HSDC Pro software to match, pressing capture causes the HSDC Pro software to throw an error that states "Start ADC to DDR, TIMED_OUT_ERROR." This only occurs after programming the EVM. Connecting and programming the VC707 without attempting to configure the ADC12J4000 yields no such error, but this doesn't allow me to test any ADC operation.

Reading some other posts has lead me to believe that it could be an issue with one of the clocks being used, but I have been unable to find out what could be wrong with the clock configuration. Another issue seems to be from a programming error when the GUI writes to the ADC, but I haven't been able to find a register that is incorrectly configured yet. It appears that the GUI is indeed setting registers correctly, and I can individually set and read control registers with no issues.

My intended operating specs for the ADC12J4000EVM GUI are:

On board Fs = 4000 MSPS

Bypass mode, DDR



ADC Output Data Rate = 4G

I currently have no analog source connected, as I would like to use a test pattern to verify my own drivers once I can be sure the modules are communicating correctly.

  • ADC12J4000_bypass_VC707 8G.pptxJeff,

    There is a second clock required by the Xilinx firmware. This LMK04828 output has to be enabled and use the correct divider. See if this document helps.



  • Jim,

    This is exactly what I needed to get it working. I had been attempting to set these registers before to see if that was the issue, but I was apparently not setting them correctly. I am now able to get some data from the ADC.

    I have, however, noticed that when I switch to certain test modes - Repeated ILA Test Mode for example - I get the same error that I was getting before. I am able to use other test modes such as the ramp test or the long/short transport test, and they appear to be correct when compared to the ADC12J datasheet.

    I'm assuming that these test modes are doing something different with the JESD transport layer that is causing the FPGA to not recognize the data. It isn't preventing me from moving forward with creating my own drivers for the TSW12J54 EVM, but I am curious as to why this could be happening.

    I have encountered another issue that I would like to clear up as soon as possible. While going through the TSW12J54 schematics, I noticed that a set of resisters (R54, R55, R57, R58, R119, R69, R120, and R121) have not been placed on the board. If I understand this correctly, this means that the SPI via FMC connections are disconnected by default. If I wanted to program the ADC over FMC rather than through the FTDI, would I need to place these components and disconnect the FTDI? I would certainly prefer to leave the FTDI intact if possible.


  • Jeff,

    You are correct about these resistors. You would not have to remove the FTDI if you want program the ADC through the FMC, only remove resistors R109, R110, R111, and R118 and install R54, R55, R57 and R58.



  • Hi Jeff

    I'm not 100% sure why the repeated ILA test mode will cause capture failures but I have a theory. I believe the capture firmware is designed to begin filling the memory buffer at the transition between the end of the ILA and the first 'normal' data. If this transition to 'normal' data never occurs that may prevent the buffer filling process from launching.

    Best regards,

    Jim B