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ADS1246 wiring

Andrew Paule
Prodigy 40 points
Other Parts Discussed in Thread: ADS1246, ADS1247

Hi -

about to release a design using a pair of ADS1246's -  I am thinking of tying the CS line to the start pin for each device.  I might need to tie both start lines high, but then I read about some of the problems with the data being tossed with the start of reads.  Any known method of using two chips for two analog signals?  I don't have the luxury of adding a line to start the things, only have SCLK (common) DIN and DOUT (common), and two CS lines - no possibility of having start line control.  I do have DRDY line from each converter, so I could just ping pong them, but I don't want to have some sort of software nightmare  

  • 0
    TI__Guru* 94285 points
    Andrew,


    I think the simplest solution would be to use an ADS1247. This device is similar to the ADS1246 but has an input multiplexer that you can use to read different channels. In this case, you'd only have a single SPI device to control instead of two and I think that alternating channels would be rather easy for control of the device.

    As for using two ADS1246's, the chip select is a /CS, so to activate the device with the START, you would need to invert the /CS to get the START polarity to start a conversion. Do you really need to power down the device? You could just use the SYNC command to force the start of a conversion. If you explain in detail what you'd like the device to do, I could offer suggestions.

    I'm not sure what you're referring to about the data being tossed at the start of reads. If you let me know what you've read (maybe point out the link), I could address your concerns.


    Joseph Wu
  • 0 in reply to Joseph Wu
    Prodigy 40 points
    I've already got a design mostly complete with the 1247 as well, but may end up expanding the number of channels and am looking for flexibility in the future as well. What caused me a bit of consternation was this forum

    e2e.ti.com/.../1763395

    It seems like there is something in the state machine that sets the DRDY pin back on receipt of an SCLK, and I will be using the DRDY as the interrupt pin in current architecture. The CS and START pins are currently tied (schematic) as I can start frames for my application on getting data from each device. I will pull the CS and START pin low at the same time, and then read the data in the output buffer, and then send them both high and wait for a DRDY on the device. This should just result in a one sample period delay on the second A/D, but when we get multiple devices in a chain it might become significant.

    Is the forum correct in that an SCLK edge will reset the DERDY pin even when the device has not been selected?

    Thanks
  • 0 in reply to Andrew Paule
    TI__Guru* 94285 points
    Andrew,


    Yes, it is correct that the SCLK edge will reset /DRDY even when the device has not been selected. I remember writing that post last year after I checked on the question.

    Just to make sure I'm following you, the conversion starts after you've taken /CS high, so you're starting a conversion after completing communication with the device. Then when you get the /DRDY indication, you pull /CS low to enable the SPI. Once you receive the data you can hold /CS and START low, which will power-down the device. Or you can pull up on /CS and START to initiate another conversion.

    Instead of using the /DRDY as an indicator, you could just use some set time period to wait for the completion of the data. If the device is set to 1000SPS, then you could wait more than 1ms to read the data out. Note that if the internal oscillator is used, then you'd need to account for the variation in the clock, which is about ±5%.


    Joseph Wu
  • 0 in reply to Joseph Wu
    Prodigy 40 points
    Sounds like my method will work for my application - I just need to make sure the software engineers never stack more than one interrupt from the A/D's Then they can go service an A/D and when out, look for the next A/D - should work. I'll give it a try

    Andrew
  • 0 in reply to Andrew Paule
    Prodigy 40 points
    If I pull the start pin low with the CS, what functions of the converter will be available - figure 70 and 113 both imply that the converter is alive and converting, and that the data out is valid.
  • 0 in reply to Andrew Paule
    TI__Guru* 94285 points
    Andrew,


    It depends on the timing. If you pull down the start pin low, the device will finish the current conversion. Once the conversion is completed, it will power down the device. You should be able to retrieve the data, but much of the converter's functions will be turned off (with the current consumption will be greatly reduced). Once the device is powered down, you will still be able to clock out the data on DOUT.

    Note that if you use the internal reference, you may need some extra time to power up the device. If the REFOUT has a large amount of capacitance, it does take time to get the internal reference back to the final value. This is described in Figure 11 of the datasheet. The time scales are typically than a single data period, and it might be seen as a gain error in the reading as it settles.


    Joseph Wu