DAC3164 FIFO Pointers / Sync Input

If you are getting FIFO collision errors or are very close to getting FIFO collision errors and SYNC is not clearing it, then I suspect that you are not using the ALIGN inputs or are not using the synconly_ena bit in register CONFIG0.   The SYNC input will reset the FIFO write pointers.  The ALIGN input will reset the FIFO read pointers.  If these are reset together then the FIFO pointers should be about centered.    If you don’t use ALIGN input, then the synconly_ena can be used to make SYNC reset both sides of the FIFO.  If the FIFO pointers are still not quite centered then the fifo_offset in CONFIG9 may be adjusted away from default to try to fine tune the FIFO centering.    There is an app note on a similar device that goes into great detail on the use of the FIFO initialization, mostly in relation to multi device synchronization but it also still applies to how the FIFOs operate.   But having a SYNC event on the FIFO in side and no similar event on the FIFO out side would not be enough I think.  Are you providing a reset event on the output side of the FIFOs using ALIGN or by setting it up to use SYNC?  If not, would you please?  That app note I mentioned is at:

http://www.ti.com/analog/docs/litabsmultiplefilelist.tsp?literatureNumber=slaa584&docCategoryId=1&familyId=82

A separate email in from the field indicates you are also trying to use the IOTEST feature but are having trouble with it.   I have used the IOTEST feature on the EVM previously, and have created a ppt document on the use of the feature that I can attach.   The IOTEST pattern test is simply that the customer can create a small 8-sample pattern file and repetitive load that pattern to the DAC.  The 8 patterns would match the 8 pre-stored IOTEST patterns, either by using the default values or by using 8 values that you have chosen to write to the registers.   Then read the SPI register that reports when a bit from the pattern coming in fails to match the expected pattern.  (Have to clear the register first that reports the errors.  Then if there are any new errors after clearing then a bit n the register will set and remain set until the next time it is cleared again.)  This requires the ability to read the SPI registers, which you are able to do since you are watching the FIFO alarms.  Ppt attached, and in that I just used the 8 default patterns and made my external sample pattern to match.   The SYNC is needed along with the sample pattern to tell the IOTEST which of the 8 samples is the first one of the 8.   The ALIGN is not needed as this feature is done before the FIFOs.     The pattern verifier compares each bit of the 8 incoming patterns against the 8 pre-stored patterns.   if there is a mismatch in any bit position, the results register is set and held for that bit position, until the results register is cleared by writing zeros.  If there are no errors, then reading the register simply reads back zero for all bits.  if there is something drastically wrong with the interface then the results register would likely return 14 ones every time it is cleared and re-read to indicate an error in every position.

 DAC3174 Pattern Test Feature.pptx

Regards,

Richard P.