I have a customer who is asking the following:
I'd like to sync DCLK (i & q) for four ADC12D1800RFs running at 1.8 GHz. Is it better to:
1) to use dclk_rst from an FPGA to two master ADCs with each master ADC syncing a single slave ADC or
2) use auto sync with a single master ADC and three slave ADCs where RCOUT1 & 2 from master goes to RCLK of two slaves, then RCOUT1 from one of the slaves goes to RCLK of a 3rd slave ADC?
Please let me know if either of these methods or possibly another method is best.
Thanks for your help with this!
Richard Elmquist
