Will the ADS7040 perform an offset calibration on power-up if chip select is held low? In my design, CS is low at power-up, for at least 16 cycles of SCLK, but there is no "first CS falling edge" (figure 37 in data sheet). CS is low from the get-go. After 16+ cycles of SCLK, then CS goes high and normal operation begins.
first CS falling edge