DAC3151 - Example and settings to get the first signal out

Mauro,

We are looking into this.

Regards,

Jim

Hi,

The only pre-made configuration file that I know of is the one that comes with the SPI GUI installer on the TI web for the EVM, as described in the User Guide for the EVM, and that brings up the DAC EVM in a common simple default state.  (and configures the clock chip that is on the EVM as well)

You mention test patterns *out* of the DAC; the only test pattern I know of is the constant value that may be entered in Config20 - the sifdac value.   Setting a value for sifdac and then setting the msb of Config20 (sifdac_ena) will cause the DAC to output a constant value.   

For more interesting outputs, such as a sine wave, the TSW1400 FPGA Pattern Generator card in conjunction with the DAC3151 EVM will allow for an easy set up of a sine wave, or two-tone pattern, or more complex patterns.   But the DAC itself does not have such patterns pre-stored.  Just the sifdac value.

If you are looking at the 8 vectors of iotest pattern, those are test patterns to test the *input* to the DAC.   A digital bit-match error tester to check the timing and robustness of the digital sample interface.    Your host FPGA would clock a repeating 8-sample pattern into the DAC with a SYNC pulse on the 1st sample of the pattern, and with iotest_ena enabled the results of the input pattern test may be read out on Config4.   I '1' in any position of Config4 indicates a bit error detected in that position of the 14 (or12 or 10) bit sample word.

For 10 bit data, as compared to the 12bit or 14 bit devices, the data is msb-justified.   The most significant bit of the sample is always on pins 10,11 of the device and for 10 bit data the four least significant bits are discarded when compared with the 14bit device. 

From what I have seen, the most common reason for not getting generic data to be output from the DAC at first is if the FIFO is not reset.   After powerup, and the DACCLK and DATACLK are present, a reset pulse on the reset pin is recommended to get all the configuration registers into their default state, and then the Write pointer address to the FIFO and the Read pointer address must be reset by a 'SYNC Event' and an 'Align Event'.   If the FIFO pointers are not reset, they may be 'stuck' as the pointers are implemented as a rotating shift register and if this powers up all zero then thee is no pointer to shift.   The ALIGN signal resets the Read pointers and the SYNC signal resets the Write pointers.   If ALIGN is not used, then the synconly_ena in Config0 may be set so that SYNC resets both sides of the FIFO.   If the SYNC signal is also not used, then there is provision to do a one-time software SYNC by setting sif_sync_ena in Config1 to 1 with sif_sync = 0, then another write to Config1 to set sif_sync = 1.     But somehow, the FIFO pointers must be reset at least once after powerup.

After that, the alarms register in Config5 is valuable.   Write a zero to that register to clear the alarms and then read the register to see if any alarms have been raised after writing zero.   If the DACCLK is not seen by the device due to improper common mode or voltage swing, then there is a DACCLK_gone alarm.  If the DATACLK is not present, then there is a DATACLK_gone alarm.   If the FIFO pointers are reset badly then there may be a FIFO pointer alarm.    any of these alarms could be used to blank the DAC output, although I think the default state is for this to not happen and you would configure the device to make the output blank in the presence of alarms if you wish.  (like if there is a power amp and transmitter after the DAC and you want to guard against transmitting garbage in the presence of a fault).  There are also 'warning' alarms that don't affect operation, such as a warning that the FIFO pointers are 2 addresses away from each other and if clocks drift any further there could be loss of data.

Offline I had received a set of config register contents from your representative.  It looked like you had the ALIGN input buffer off but also had synconly_ena set which takes care of the ALIGN side.  Good.   It looks like the SYNC buffer is on, so I presume you have a SYNC pulse at some point on the SYNC input.  If you are not seeing Alarms in Config5 then you should see data output.  

Your pattern data after this would just be a continuous stream of sample data.  If you send a test pattern like a sine wave, you may want to create such a pattern of samples of some arbitrary length and have your FPGA loop through the pattern repetitively.  That is what our TSW1400 can do.   A SYNC pulse is commonly used on the first sample through the pattern, but if there is a SYNC *every* time through then make sure the pattern length is divisible by 8 so that the SYNC pulse comes along to 'reset' the FIFO to a position that the FIFO is already in and there is no disruption of data.  Else, just SYNC the FIFO once and be done with it.

Regards,

Richard P.

Thanks for your inputs.

Ciao,

SunSet