How to execute a calibration of ADC12D18000

Hi Xiaolu

Can you also provide an FFT plot showing the spectrum you see with FIN and the 2IN-FS spur identified?

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Thanks,

Best regards,

Jim B

Hi Jim B

   Thank you for your reply！

  Detailed information please refer to the word documentation, wait for your good news。

  Best regardsadc12d1800-Consultation20160926.doc

Hi xiaolu

I gathered data using the ADC12D1800RB at 500 MSPS. Here are the results:

/cfs-file/__key/communityserver-discussions-components-files/73/4137.ADC12D1800-500MSPS-Fin-260-and-408.pdf

You have identified your large spur location as 2Fin-Fs. 2Fin is the second harmonic, and due to Nyquist folding will fall in the spectrum at 2Fin-Fs. I expect this is the spur that is being seen in your testing. Likely causes of H2 are poor balance in the input signal path differential layout/routing, or H2 in the signal applied to the circuitry. Since the other harmonics look OK I think the calibration process is generally working OK.

Can you send plots showing your input signal routing? I may be able to identify sources of imbalance there.

Do you have a lowpass or bandpass filter to remove harmonics from the RF signal generator output? If there is no filter on the signal from the generator that could definitely be the cause.

Best regards,

Jim B

Hi Jim B

   Thank you for your reply.

  Document which illustrates the principle of AD design and PCB design,

3603.adc12d1800-SCH&PCB 20160927.doc

Clock design

2117.erf_clk_lmk04_201608025.pdf

Hi xiaolu

Thank you for the additional information.

From the layout plots I see that you have 2 ADC12D1800 devices on your board, and the layout routing from the balun outputs to the ADC inputs is somewhat different for each of the 4 input channels.

Can you provide FFT plots showing the same input signal frequency being captured using each of the ADC inputs (only apply the signal to the one channel being tested). That might tell us if the issue is common to all channels, or related to the input signal routing of a specific channel. If it is due to specific channel signal routing, please review the information in the following document regarding optimizing this aspect of the design.

"Schematic and Layout Recommendations for the GSPS ADC"  http://www.ti.com/lit/pdf/snaa206

Best regards,

Jim B

Hi Jim B

Thank you for your apply.

The spur is commom to all channels,so I don't think it's a PCB layout.

     We use the environment mainly has three kinds. The first ,when the sampling rate is set to 500MSPS, the input frequency is 275Mhz~475Mhz. The Second , when the sampling rate is set to 1000MSPS, the input frequency is 550Mhz~950Mhz.      The Third,   the sampling rate is set to  2Gsps, the input frequency is 1100Mhz~1900mhz.

Please tell me how to choose the bandpass filter or low pass filter design.

Now,I have no way to solve it.

Please help me to find out the reason.

Thank you.

Best regards

Hi Xiaolu

The filter I was referring to would be used in your lab validation setup in between your RF test signal source and the board being tested. This filter is to reduce the harmonic distortion typically output by even high quality RF signal generators. I would recommend that you connect your RF signal to a spectrum analyzer to quantify the 2nd harmonic power level in that signal to confirm that the spur you see in the ADC FFT is not included in the test signal you are applying to the ADC.

If the VIN and CLK routing are implemented well (no imbalances or impedance discontinuities, no coupling between VIN and CLK) you should not be seeing a spur at 2Fin-Fs at that magnitude.

Best regards,

Jim B