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ADS9110 Zone 2 operation and SNR performance

Mo.
Mastermind 22165 points
Other Parts Discussed in Thread: ADS9110, ADS9110EVM-PDK

Hello Team,

We received the below questions from one of our customers on the ADS9110 device:

This part is still under review. We were going to implement Zone 2 data transfer as per page 28/29 (figure 50 of the ADS9110 datasheet) with clock speed 43 MHz but would like to know more now after coming across the note on page 30 of the ADS9110 datasheet. The note states that the device's SNR performance is degraded in this mode as the data transfer is active during data conversion.

The device was selected for its SNR performance and it's important that we achieve high SNR. Is it possible for you to find out if there is anyway we can achieve the maximum throughput (2MHz application) without compromising the SNR and if there is no other way what would be the degradation we are likely to see if we implement Zone2; 43MHz operation.

We also came across the "Output clock source options with SRC PROTOCOLS" on page 36. Is it an option to achieve the 2MHz performance without compromising the SNR. We are not keen to implement high speed SCLK as we have 24 ADCs on one board and it is difficult for us to implement clock distribution with 0/minimal delay between clock and data paths.

Can you also find out that if the EVAL board and the accompanied software will allow us to evaluate the Zone 2 operation and the SNR (SNR degradation) performance and if so how I do this please?

Thank you in advance!

Kind regards,

Mo.

  • 0
    TI__Guru 55466 points

    Hi Mo,

    Discussed with other engineers, one alternative is to setup the device in dual SDO mode and shift the data immediately after the end of sampling, as CONVST toggles high - (while meeting the quiet time requirements) in normal SPI mode. It will take ~220 ns to shift the 18 bits of data using a 43 MHz clock. This leaves approximately 100ns of quiet time before the end of conversion.  When using this configuration, since there is no digital activity during the last 100ns of the conversion period, no SNR degradation occurs.

    Another alternative is to use single SDO mode, but customize the clock pattern such that there is no SDO activity around the end of conversion (which is indicated by the BUSY/READY signal). Making sure that there is no SDO toggling for a period of 100ns before the READY goes high should be sufficient to avoid SNR degradation. The user should be able to capture all the 18 bits @ 43 MHz clock in this mode.

    The ADS9110EVM-PDK evaluation kit firmware supports Zone1  operation; with Single, Dual or Quad SDO.  I will follow with you directly via email with this request. 

    Thank you and Kind Regards,

    Luis