This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Setting register on ADS8556EVM

Other Parts Discussed in Thread: SN74AHC138, ADS8556

Dear TI E2E community,

I am using an ADS8556EVM in the software mode with serial interface. I'm not be able to read register. In fact I always read  0x7FFE7FFE.

What could be the culprit?

Thanks!

Best regards,

Alessio Igor Bogani

  • Hi Alessio,
    Thanks for selecting TI ADC, are you using your own CPU or controller board to test with ADS8556EVM? What's the hardware connection and configuration? What's your software flow? Your more information will be useful and helpful. Thanks.

    Regards
    Dale
  • Hi Dale,

    I use a BeagleBoneBlack (BBB) with Linux (4.7) and the two boards (BBB and ADS8556EVM) are connected with a very simple circuit:

    AD58556EVM.pdf

    ADS8556EVM's SW1 switch is so configured:
    Left (Byte)
    Right (Range 4x)
    Left (SFT)
    Left (SER)
    Left (Refbuf ENA 1)
    Right (Daisy chain ENA 0)
    Left (SERA Enable 1)
    Right (SERB Enable 0)
    Right (SERC Enable 0)
    Right (Refen 0)

    The Linux kernel SPI driver is configured with SPI_CPOL=1 and SPI_CPHA=0 (SPI mode 2).

    So I write through SPI 0xE00303FF and I always receive 0x7FFE7FFE back.
    I also tested to assert RESET pin (HIGH -> LOW) but the answer doesn't change.

    Thanks for your help!

    Best regards,
    Alessio Igor Bogani

  • Hi,

    Are needed further information?

    Thank you!

    Best regards,

    Alessio Igor Bogani

  • Hi Alessio,
    I apologize for my late response, I missed your feedback for some reasons.

    Firstly, you will have to make sure your hardware connection and pin configurations are correct:
    1. For software and serial mode, some pins will have to be pull up high or pull down low, for example:
    Pin 29 (WORD/BYTE) should be connected to BGND (you configured SW1.1 to left for byte which is high to Pin 29)
    Pin 20 (/RD) should be connected to BGND
    Pin 12/13/14 (DB5/4/3) should be connected to BGND (DCEN=0)
    Pin 5/6 (DB10/9) should be connected to BGND (SEL_C/B=0)
    2. Make sure the standby(/STBY) input is high, the /STBY signal on ADS8556EVM is controlled through a 3-8 decoder SN74AHC138. By default, /STBY is low. There are pull up resistors(R15,R34,R35 and R36) on the select input and pull down resistor(R33) on the enable input of SN74AHC138, the combination of these inputs creats a logic low on Y7 which is /STBY input to ADS8556. Use jumpers on J4 to bring Y7 to high.
    3. You are using your chip selection signal from your BBB CPU/MCU board to J1.7 on ADS8556EVM, please make sure a jumper on Pin 7-8 of JP3 to connect it to /CS of ADS8556. If your CPU/MCU cann't sink the current to pull the pin low you can consider removing the pull up resistor(R18).

    Your SPI configuration(CPOL=1,SPI_CPHA=0 - SPI mode 2) should have no problem because the output data are changed at the rising edge of SCLK so that the host processor can read it at the following falling edge, also the serial data input SDI are latched at the falling edge of SCLK.

    Can you please follow up timing in the Figure 42 of ADS8556's datasheet to send more update commands? then check the data on the SDO, also please check if have any BUSY output if possible. It will be better if you can provide a screen shot of SCLK and SDI along with FS/CS during your initialization cycle.
    Thanks.

    Regards
    Dale

  • Hi Dale,

    No need to apologize!

    So there are all information that I be able to gather:

    Avdd= 5V (TP3)

    Dvdd=0V (TP8)

    Bvdd=3.38V (TP16)

    +Vin=15V

    -Vin=-15V

    HVSS=15V

    HDSS=-15V

    A0=A1=B0=B1=C0=C1=0V

    JP12 on

    TP10=2.5V

    JP9 HOLDx all to J4.17

    (I have tried also with HOLDA to J4.17 and HOLDB=HOLDC=GND, with no difference)

    JP3: J1.7 on

    Y3 off

    Y2 off

    Y1 off

    We have provided an external clock (0-3.3V 18MHz 50%DC) but there were non difference with or without clock.

    We have performed the test on 3 different ADS8556EVM, purchased from different suppliers.

    We have also tried to operate the EVM using hardware mode. The captured waveforms where slightly different depending on different sequences and different configuration of the EVM, but anyhow we could not see the BUSY signal (J4.19 on EVM) going low after a convst pulse (that is 300us long).

    Our setup:

    1. Test performed:

    We have used the spidev_test utility in order to control the spi0 channel of an BeagleBoneBlack.

    We have prepared a script to test a simple acquisition from the ADS8556

    echo "------------ new run ---------------"

    #to be sure that the initial states are the correct ones
    echo 0 > /sys/class/gpio/gpio32/value
    echo 0 > /sys/class/gpio/gpio36/value

    #reset
    echo 1 > /sys/class/gpio/gpio36/value
    echo 0 > /sys/class/gpio/gpio36/value


    echo "everything as default, no convertion"
    ./spidev_test -vOD /dev/spidev1.0 -p "\x00\x00\x00\x00" -s 1000000


    echo "same settings, set convertion on channel A"
    ./spidev_test -vOD /dev/spidev1.0 -p "\x30\x00\x00\x00" -s 1000000

    echo "convst"
    echo 1 > /sys/class/gpio/gpio32/value
    echo 0 > /sys/class/gpio/gpio32/value

    echo "read chA and set no convertion"
    ./spidev_test -vOD /dev/spidev1.0 -p "\x00\x00\x00\x00" -s 1000000

    Running the script we have got

    ------------ new run ---------------
    everything as default, no convertion
    spi mode: 0x2
    bits per word: 8
    max speed: 1000000 Hz (1000 KHz)
    TX | 00 00 00 00 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  | ....
    RX | 7F FE 7F FE __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  | þþ
    same settings, set convertion on channel A
    spi mode: 0x2
    bits per word: 8
    max speed: 1000000 Hz (1000 KHz)
    TX | 30 00 00 00 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  | 0...
    RX | 7F FE 7F FE __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  | þþ
    convst
    read chA and set no convertion
    spi mode: 0x2
    bits per word: 8
    max speed: 1000000 Hz (1000 KHz)
    TX | 00 00 00 00 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  | ....
    RX | 00 00 00 00 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  | ....

    Capturing the waveform with a Rigol scope (logic analyzer mode):

    Zooming to the details:

    Busy goes low few ns after reset:


    Busy goes high few ns after convst


    SPI Reading/writing:


    Zooming closer:


    Please let me know If I missed to post some information.

    Thank you!

    Best regards,

    Alessio Igor Bogani

  • Hi Alessio,

    Thanks for your information, BUSY signal could not be seen, it means that ADC did not work, I still have some questions to figure out the root reason:

    1.  Can you please let me know how long for CONVST pulse high and Busy high after CONVST? I can not see them clearly from the screenshots.

    2.  When the screenshots were captured, was the BUSY seen with any change or kept high all the time?

    3.  Can you check /STBY signal on ADC or pin7 of U3?

    4.  As mentioned before, the correct pin configurations have to be guaranteed before the tests. For serial mode, some pins will have to be pull up high or pull down low, for example: 
         Pin 29 (WORD/BYTE) should be connected to BGND (you configured SW1.1 to left for byte which is high to Pin 29)
         Pin 20 (/RD) should be connected to BGND
         Pin 12/13/14 (DB5/4/3) should be connected to BGND (DCEN=0)
         Pin 5/6 (DB10/9) should be connected to BGND (SEL_C/B=0)

    Please check pin functions table in datasheet for details.

    4. XCLK input depends on CR bits, Software mode (HW/SW = 1): External conversion clock input, if CR bit C11 (CLKSEL) is set high or internal conversion clock output, if CR bit C10 (CLKOUT_EN) is set high. If not used, connect to BVDD or BGND. By default, these bits are low in CR register.

    Thanks and waiting for your more information.

    Regards

    Dale

  • Hi Dale,

    1) We performe a simple test:
    - we reset the board, so BUSY reset.
    - we enable the conversion from A, B and C channels sending 0xE0000000 to the control register
    - we set the CONVST, BUSY goes high and remain high until we reset the board

    2) Busy goes low after a RESET, any time we rise the CONVST it goes high and remain high until next reset (seconds or minutes).

    3) You have got a point there!!!! Yes, /STBY signal was down.......
    We left unconnected pins J4.1, J4.7, J4.9, J4.11, J4.13, so U3.7 was low. Now we fix it connecting DC_A0 to GND

    4) We fix it according to your suggestion.

    Set /STBY to 1 work it out! Now Busy goes low after something more than a us and the ADC is acquiring data.

    Thank you very much!
  • Hi Alessio,

    I'm glad to hear that you have verified and figured out the root reason on ADS8556EVM, please let us know if you have more questions for our SAR ADC.Thanks.

    Regards

    Dale