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Unable to lock LMK04828 on ADC12J1600 EVM.

Madhubabu Anumukonda
Prodigy 50 points
Other Parts Discussed in Thread: LMK04828, ADC12J1600, LMX2581, TRF3765

Hi,

I'm working on ADC12J1600 EVM to interface with my FPGA development kit.  The EVM uses the LMK04828 for JESD204B clocks.  I am programming the registers using ADC12J1600 EVM GUI with following configuration for 2Gbps lane rate.

Clock source = onboard, 

Fs=1600 MSPS,

decimation  and serial mode = decimate-by-16, SDR; P54.

With this configuration,  I able to see the lock detect on LMX2581 (LD pin) but unable see the lock detect on LMK04828(status_LD1, status_LD2 pins).  Could  you please tell me,  why LMK04828 not detecting the lock for the above configuration.

Thanks,

Madhubabu

  • 0
    TI__Mastermind 43830 points

    Hi Madhubabu

    I'm assuming you have the earlier revision of the ADC12J1600EVM since you mention the LMX2581. In that version of the EVM the configuration file for the LMK04828 did not program the LD1 and LD2 logic levels properly. So the LED status is not indicative of the proper or improper function of the LMK04828.

    In that board and the newer revision, the LMK04828 PLLs are not used. The LMX2581 (TRF3765 on newer Rev A EVM) is used to create the ADC clock, and an input clock for the LMK04828. The LMK04828 is used in distribution mode to generate the FPGA Clocks and SYSREF from this input clock.

    Since you are using this EVM with an FPGA development kit, I also wanted to point out another detail. The JESD204B data lanes on the ADC12J1600EVM are inverted with respect to the standard FMC pinout. This was done to make signal routing easier. The firmware and software used with the TSW14J56EVM compensates for this polarity inversion. Please make sure that your firmware is configured to compensate as well. Here is a recent post discussing this issue:

    https://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/p/537893/1961555#1961555

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 50 points

    Hi Jim,

    Thanks for your reply.

    Yes. I am using earlier version of ADC12J1600 EVM which has LMX2581 for ADC Clock and input clocks for the LMK04828. Also I am taking care the polarity inversion in FPGA code at Receiver side.

    Before going to the JESD204B protocol testing, I want to check whether PLL’s are lock status and generate the clocks correctly to ADC’s and JESD204B IPs. I configured the EVM with for 2 Gbps lane rate, by selecting  onboard clock, Fs = 1600 MSPS - Decimated by 16-SDR-P54 mode.

    Could please tell me is there any mechanism to confirm the LMK04828 PLL lock status and clock generation for the above configuration.

    Thanks,

    Madhubabu

  • 0 in reply to Madhubabu Anumukonda
    TI__Mastermind 43830 points

    Hi Madhubabu

    If you are using Internal Clocking mode and Fs=1600 MSPS and then clicking on the Program Clocks and ADCs button you can assume the LMX2581 is locked, and that the clocks coming out of the LMK04828 are correct. As I stated earlier, the PLLs in the LMK04828 are turned off, it is only performing divide and synchronization functions.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 50 points

    Hi Jim,

    I  measured the clock frequency coming from the LMK04828(internal clock Fs=1600 MSPS, DB16,SDR) to FPGA and it is ~48 MHz. But  I need 100 MHZ to my FPGA for 2 Gbps lane rate. For this I tried the different divider values and unable to get the 100 MHz FPGA clock.

    Could please provide the correct configuration for 2 Gbps lane rate at my FPGA SERDES lanes.

    Thanks,

    Madhubabu

  • 0 in reply to Jim Brinkhurst1
    Prodigy 50 points
    Hi Jim,




    I measured the clock frequency coming from the LMK04828(internal clock Fs=1600 MSPS, DB16,SDR) to FPGA and it is ~48 MHz. But I need 100 MHZ to my FPGA for 2 Gbps lane rate. For this I tried the different divider values and unable to get the 100 MHz FPGA clock.

    Could please provide the correct configuration for 2 Gbps lane rate at my FPGA SERDES lanes.





    Thanks,


    Madhubabu
  • 0 in reply to Madhubabu Anumukonda
    TI__Mastermind 43830 points

    Hi Madhubabu

    I assume you have P54=1. If P54=0 the line rate is 1600 Mbit/sec, not 2000. At 1600 MSPS in DB16 mode, 2Gbps line rate corresponds to DDR=0, P54=1. Line rate is 1.25x Fs = 2000.

    For that mode the EVM should be currently configured to provide an FPGA clock of LineRate/10 or 200 MHz.

    To achieve 100 MHz FPGA clock, the dividers at LMK04828 Registers 0x100h and 0x110h  should be changed to 0x10h (16 decimal). They are currently 0x08h. You can edit the file LMK04828_DB16_SDR_P54_Fs_2480Msps.cfg with these updated values and they will be automatically loaded when you choose this mode and sample rate. The file should be located in this folder: C:\Program Files (x86)\Texas Instruments\ADC12J1600EVM GUI\Configuration Files

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 50 points
    Hi Jim,

    I able to generate the 100 MHz clock. Thank for your support.

    Regards,
    Madhubabu