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ADC3423 DCLK rate

Nir Flysher
Expert 3347 points
Other Parts Discussed in Thread: ADC3423

Hi Team,

We want to work with the ADC3423 at 80MSPS using two-wire LVDS at 480MSPS.

What should be the DCLK rate ? 80/120/480 ?

What should be the relationship between the DCLK and CLKIN ?

Best regards,

Nir.

  • 0
    TI__Genius 12965 points
    Nir,

    The ADC342x operating in 2 lane mode (6x serialization) will have a DCLK that is 3x the sample rate (DDR clock - samples on every edge, results in 6 bits serialized on 2 lanes per sample clock). So in this case with a sample rate of 80Msps the DCLK should be 240Msps.

    Ken.