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ADS5444

Michele Santorsola
Prodigy 10 points

I have SI simulation problems on the clock input signal of the ADC.

The circuit is described in the attached file "TOPOLOGY_ADC_CLKA.pdf"

Driver: SN65EPT22DGK (pin 1 and 2)
Receiver:ADS54444IPFP (pin 10 and 11)
Signal differential lvpecl, frequency: 33MHz
The simulation results are described in the attached file "SIMULATION_ADC_CLKA.pdf"

 In detail:

The differential signal LVPECL are coupled in ac.

For each single signal in input to ADC, common-mode voltage is fixed to 3.5V vs 2.4V (value on datasheet).

The differential signal in input to ADC  is not centered on the logical levels (low and high)

Why?

/cfs-file/__key/communityserver-discussions-components-files/73/2844.TOPOLOGY_5F00_ADC_5F00_CLKA.pdf

/cfs-file/__key/communityserver-discussions-components-files/73/7077.SIMULATION_5F00_ADC_5F00_CLKA.pdf

  • 0
    TI__Mastermind 29220 points

    Hi,

    thank you for providing the circuit topology you are simulating, and the simulation results.  We will look into this.   I do not know what the problem could be at the moment.   I see that this ibis model was created quite some time ago, and we no longer have access to the tools that we first used to create the model.  So I will have to have the design team look into this as best we can. This may take a bit of time but I will keep you posted.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    TI__Mastermind 29220 points

    hi,

    I also notice that the signal is unterminated at the end of the line before the ADC.  This would explain the ringing on the silulation results.  You have the driver, about 2mm of board trace to the 150 ohm pulldowns, and then about 16cm of trace to the ADC that is unterminated which is a pretty long stub and will generate reflections.   The ADC does *not* include the 100 ohm termination or two 50 ohm terminations so this termination should be external.  I would add a 100 ohm resistor after the AC coupling caps across the pair and see what that does to the simulation.  it should clean it up a lot, but maybe not fix the issues with the levels of the signals.  But I would suggest to debug it in steps.  Remove the ADC model and put a simple 100 ohm resistor there.   Then add a 1K ohm resistor to a 2.4V voltage on each side of the signal to see that the rest of the testbench converges to the expected result.  Then if the simulation does behave as expected replace the two 1Kohm biasing resistors with the original ADC model again.  But if the testbench does *not* behave as expected with the simple 1 Kohm biasing to 2.4V, look to see if there is an issue with the testbench setup.  And if the testbench *does* behave as expected then it has to the ADC model.    if I can get Hyperlynx installed on my PC I could try to replicate.  We have a site license here for Hyperlynx but the install hung up so I have to address that first.

    Regards,

    Richard P.