Is it possible to load two TLV5610 devices by daisy chaining the DIN / DOUT pins and using one frame sync (in uC mode). That is, will the device pass the shifted data applied to DIN to DOUT delayed by 16 SCLKs without FS being applied. This would allow the downstream 16 bits to be presented at the same time the upstream device sees the next 16 bits. We would assert FS after 16 bits and both devices would then clock in their data correctly. The first from the FPGA and the second from the delayed 16bits driven from the DOUT of the first. Is this correct?
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