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DAC34H84

new2day
Expert 1940 points
Other Parts Discussed in Thread: DAC34H84, LMK04803, DAC5687

It's about multi-device SYNC.

We have two DAC devices DAC34H84 on the board.

In our case,

1. both DACCLK (DAC clock not data clock) and OSTR are from the same PLL (LMK04803) to two DAC devices.

2. All OSTR are aligned and aligned to the DACCLKs too. 

3. DAC PLL is not enabled. 

We set-up DACs according to POWER-UP SEQUENCE (refer to page68-71) as well as what stated in page 50 to 51, which is MULTI-DEVICE SYNC without PLL (PLL BYPASSED).

However, however we still got "1 away" and or "2 away" alarm. The outputs from two devices still have phase delta, means they are not aligned. 

Any ideas? Thanks a lot. 

Additionally, ISTR is used for FIFO IN etc.

  • 0
    TI__Guru* 91947 points

    New2day,

    We are looking into this.

    Regards,

    Jim

  • 0
    TI__Guru* 78174 points

    new2day,

    Please refer to app note below, section 2.5, on FIFO adjustments in dual sync setup.

    -Kang

  • 0 in reply to Kang Hsia
    Expert 1940 points

    It doesn't help. 

    Here are some funny observations:

    1. observed 4nS between two DAC devices when configured as below,

    1) set both DAC Data clock and DACCLK at 250MHz, no DUC (RAW data)

    2) FIFO are disabled

    3) registers 0x1E, 0x1F and 0x20 stay at their defaults

    3) same ISTR to both DAC chips

    2. observed also 4nS between two DAC devices when configured as below

    1) set both DAC Data clock and DACCLK at 250MHz, no DUC (RAW data)

    2) FIFO enabled

    3) registers 0x1E and 0x1F stay at their defaults while 0x20 was set to x"2201" that's single source SYNC mode

    4) no FIFO alarm from register 0x5 

    3. observed also 4nS between two DAC devices when configured as below

    1) set both DAC Data clock and DACCLK at 250MHz, no DUC (RAW data)

    2) FIFO enabled

    3) set registers 0x1E, 0x1F, 0x20 and 0x00 as the Table 8 in "slaa584", especially step 30 to 42 in the Table

     

    By doing the same above and set interpolate to 2 and DACDCLK from 250MHz to 500MHz (no mixer), the time delta changed to 8nS instead of 4nS. 

    I'm running out of ideas now!

    Our design and PCB layout are very carefully done for the high speed and synchronous operations, in which

    1. all LVDS buses (Data/ISTR/SYNC etc) well matched in length between two chips 

    2. OSTR and DACCLK are well matched between two chips and they from the same PLL

    3. OSTR and DACCLK P/N leg things have been taken in consideration agaist the datasheet

    4. DAC Data clocks are sourced from the same PLL as OSTR and DACCLK 

    5. so on and so forth. the same scheme have been implemented on all our products and we never have this alignment issue 

    -- for example, with DAC5687 etc . . .

  • 0 in reply to Kang Hsia
    Expert 1940 points
    It doesn't help.

    Here are some funny observations:

    1. observed 4nS between two DAC devices when configured as below,

    1) set both DAC Data clock and DACCLK at 250MHz, no DUC (RAW data)

    2) FIFO are disabled

    3) registers 0x1E, 0x1F and 0x20 stay at their defaults

    3) same ISTR to both DAC chips

    2. observed also 4nS between two DAC devices when configured as below

    1) set both DAC Data clock and DACCLK at 250MHz, no DUC (RAW data)

    2) FIFO enabled

    3) registers 0x1E and 0x1F stay at their defaults while 0x20 was set to x"2201" that's single source SYNC mode

    4) no FIFO alarm from register 0x5

    3. observed also 4nS between two DAC devices when configured as below

    1) set both DAC Data clock and DACCLK at 250MHz, no DUC (RAW data)

    2) FIFO enabled

    3) set registers 0x1E, 0x1F, 0x20 and 0x00 as the Table 8 in "slaa584", especially step 30 to 42 in the Table



    By doing the same above and set interpolate to 2 and DACDCLK from 250MHz to 500MHz (no mixer), the time delta changed to 8nS instead of 4nS.

    I'm running out of ideas now!

    Our design and PCB layout are very carefully done for the high speed and synchronous operations, in which

    1. all LVDS buses (Data/ISTR/SYNC etc) well matched in length between two chips

    2. OSTR and DACCLK are well matched between two chips and they from the same PLL

    3. OSTR and DACCLK P/N leg things have been taken in consideration agaist the datasheet

    4. DAC Data clocks are sourced from the same PLL as OSTR and DACCLK

    5. so on and so forth. the same scheme have been implemented on all our products and we never have this alignment issue

    -- for example, with DAC5687 etc . . .