• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 47 subscribers
  • Views 1027 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Sysref in ADC3423

Izik
Expert 1565 points

Hello 

I don't fully understand the role of the SYSREF signal in the ADC3423. 

Is it needed only for part to part synchronization? If i have only one ADC can I leave the SYSREF pins open? 

Is there a way to synchronize multiple ADC's without sysref? 

The internal drawing in the datasheet is not clear. I don't undertand the direction of the lines. Is the sysref goes in or out from the divider? can you show a more detalied drawing with explanation? 

Thanks for helping

  • 0
    TI__Genius 12965 points
    Izik,

    Yes it is similar to a sync. It can be used to reset the counters and dividers in the device if you want to do some synchronization. It is not the same function as JESD204B.

    If you do not need this, please ensure that it does not float as this could cause some issues with noise causing a logic transition which will reset the device and cause glitches. Normally you can tie this to a static logic level (M to gnd and P to DVDD) or disable the SYSREF BUF in the register map.

    Ken
  • 0 in reply to Ken C
    Expert 1565 points
    Hi Ken

    Thank you for your answer.
    Where can I find more information on the sync method? Timing between sync signal and counters/dividers reset? Any timing diagrams? application note? Which dividers and counters are being reset?

    Can you please elaborate on the drawing I've attached in the previous post?

    Thanks
    Izik
  • 0 in reply to Izik
    TI__Genius 12965 points

    Izik,

    The SYSREF will reset the divider so that the divider output will be the same phase across multiple ICs.

    If you are not using the divider or not trying to do multi chip synchronization then you can just disable the SYSREF BUF.

    Ken

  • 0 in reply to Ken C
    Expert 1565 points
    Actually I am intending to synchronize 3 adc's, so any information regarding this issue will help.
  • 0 in reply to Izik
    TI__Genius 12965 points
    Izik,

    Just ensure that you match the clocks, SYSREF and data lines to each ADC. Also ensure that your SYSREF signal meets setup and hold times as defined in the data sheet. This will ensure that you can synchronously reset each of the ADCs.

    Ken.
  • 0 in reply to Ken C
    Expert 1565 points

    Would be possible to have the sync signal generated by the FPGA from the same clock as the adc uses,  and not necessarily from LMK clock distribution device?

  • 0 in reply to Izik
    TI__Genius 12965 points
    Izik,

    You just need to meet setup and hold times between ADC clock and SYSREF signal. LMK as source for both will ensure this, but if you can guarantee this some other way then it is ok. I cannot tell you if a signal from FPGA is good enough.

    Ken
  • 0 in reply to Ken C
    Expert 1565 points
    Thanks
  • 0 in reply to Ken C
    Intellectual 260 points
    Ken,

    I had same question. and I understand about the SYSREF with your answer.

    By the way,

    WHY Data sheet lacks the description about the SYSREF ?
    It must be includes the notice like you wrote here.

    Many user will asks periodically same question until the datasheet revises.
    I hope it added in next doc rev.

    Hiro