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ADS7040 QUESTION - Chip select pin

Other Parts Discussed in Thread: ADS7040


Customer want to get confirmation if it is no problem to connect CS pin to low (GND) continuously for the operation..

In datasheet, I saw it should be falling edge and rising edge for one cycle data out.. Thanks.. 

  • Hi Jung-Ho,

    In the case of the ADS7040, the CS pin is used to activate the SPI interface and to trigger the SAR ADC conversions; and therefore it is not possible to leave CS pin low for continuous conversions.   

    The ADS7040 is a SAR ADC, where the conversion cycle has two phases: an acquisition phase and a conversion phase. The device is by default on the acquisition phase, where the external circuitry is allowed to charge the ADC’s sample-and-hold capacitors to a level proportional to the analog input. Conversion begins at the CS falling edge when the signal is sampled. During conversion, the sample-and-hold capacitors are disconnected from the analog input, the signal is sampled and converted to a digital code with the CDAC. After the conversion period lapses, the sampling capacitors are reconnected across the AINP and AINM pins and the ADS7040 returns to acquisition phase.

    Please refer to Figure 1 on p.7 and section 8.1 p.14 of the datasheet for more information.

    Please let me know if you have any questions,

    Thank you and Best Regards,


    ADS7040 Datasheet:

  • Dear,

    Thanks for rapid confirmation on my question.. Thanks again.