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ADS7841 offset

Maxime ATHEE
Prodigy 740 points
Other Parts Discussed in Thread: ADS7841

Dear all,

Please find below a question from my customer, could you please clarify the concerns ? 

We have an offset of 155 mV in the ADS7841 we are using, please see table in my email below. According to TI data sheet we would expect an offset of 1.22 mV, i.e. 127 times smaller, i.e., we are getting an offset 127 times larger than the one indicated in data sheet? Has this any explanation?

Best regards,

Maxime

  • 0
    TI__Expert 3785 points
    Hi Maxime,

    I am not able to see the email which you referred to in your post.

    Could you please share the schematic and operating conditions such as VREF, VDD and throughput?

    Also, as you pointed out that Offset is 127 times larger than expected, it could happen because the captured data from the ADC is left shifted by 7 bits. Left shifting of data by 7 bits will yield a multiplication factor of 127.

    It would be helpful if you could provide oscilloscope plots showing CS, DCLK, DIN, BUSY and DOUT when Vin = 0V. In case all of these cannot be captured simultaneously, you could capture two sets - [CS, DCLK, DIN, BUSY] and [CS, DCLK, DOUT, BUSY] when Vin = 0V.

    Regards,
    Rahul
  • 0 in reply to RahulVK
    TI__Prodigy 740 points

    Hello Rahul,

    Please find below the table,

    Input Voltage  ADC  |||   Output ADC * Vref (3V)

    0 mV                |||                 0 mV

    155 mV            |||                0 mV

    1.5 V                 |||                1.345 V

    3 V                    |||                2.845 V

    I will forward the post to my customer to give you additional data

    Thanks, Maxime

  • 0 in reply to Maxime ATHEE
    TI__Expert 3785 points

    Hi Maxime,

    Looking at the table, I can say that this is not 7-bits getting shifted out. Hence the oscilloscope plots for digital pins will not be necessary.
    Could you please provide schematics and information on operating conditions?

    Regards,
    Rahul

  • 0 in reply to RahulVK
    Prodigy 10 points
    Thank you very much Rahul,
    After investigation the problem is in an FPGA or our supplier (HW developer), which processes the ADC output. I apologize because our supplier was reading the value at the FPGA output and not at the FPGA output!
    In the end the supplier discovered an obvious error in the FPGA.
    You helped us a lot with your support but we should have seen the problem before contacting you.
    I am sorry I bothered you with this, but thank you again because your answer put us on right track, which we should have taken before.
  • 0 in reply to Avelino Martin
    TI__Expert 3785 points
    Hi Avelino,

    Thanks for the update.
    It is good to know that the issue is resolved.

    Regards,
    Rahul