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ADC342x PSRR and SFDR

Lolo
Prodigy 250 points
Other Parts Discussed in Thread: ADC3423

Hello,

If I want to get an SFDR better than 60 dBc for the ADC3423, close to a zero IF signal, what is the max amplitude ripple allowed at the analog Vdd and digital Vdd ?

The PSRR is lower at the very low frequencies of the ADC, so let's take the worst case PSRR = -25 dB.

Thanks

Laurent

  • 0
    TI__Mastermind 44560 points
    Hi Laurent
    Most of the support team is out of office for the US Thanksgiving holiday. Someone will be able to respond to this early next week.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Prodigy 250 points

    Hello,

    Do you have an answer ?

    Thanks

    Laurent

  • 0 in reply to Lolo
    TI__Prodigy 370 points
    Laurent,

    I am waiting a response on the design team for how they calculated PSRR for this device... I'll let you know as soon as I hear back.

    Thanks,
    Dave
  • 0 in reply to David Guidry
    TI__Prodigy 370 points
    Laurent,

    Sorry for the long delay. I received word back on the PSRR calculation. To estimate the impact of PSRR, use the following relationship

    20*log10(Vpowersupply_tone/Vadc_fullscale) (dBFS) + PSRR(dB) = degradation in overall noise floor(dBFS)
    20*log10(50mVpp/2Vpp) (dBFS) + PSRR(dB) = degradation in overall noise floor(dBFS)
    -34dB - 25dB = -59 dB

    This calculation gives an estimate of the sum of tones that will result from ripple on the power supply (including fin+/-fpsrr and fpsrr). SFDR will be slightly better, but it would be safe to assume that if the amplitude of the PSRR ripple is less than 50mVpp on each supply, you should hit your SFDR goal.

    Please let me know if you have any more questions.

    Thanks,
    Dave